| 1 |
[p AUTOSTATIC LARGE_MODEL SMALL_DATA LFSROK EMI_WORD ]
|
| 2 |
"19 C:\Programmer\HI-TECH Software\PICC-18\9.50\include\errata.h
|
| 3 |
[e E1 .
|
| 4 |
ERRATA_4000 1
|
| 5 |
ERRATA_FASTINTS 2
|
| 6 |
ERRATA_LFSR 4
|
| 7 |
ERRATA_MINUS40 8
|
| 8 |
ERRATA_RESET 16
|
| 9 |
ERRATA_BSR15 32
|
| 10 |
ERRATA_DAW 64
|
| 11 |
ERRATA_EEDATARD 128
|
| 12 |
ERRATA_EEADR 256
|
| 13 |
ERRATA_EE_LVD 512
|
| 14 |
ERRATA_FL_LVD 1024
|
| 15 |
ERRATA_TBLWTINT 2048
|
| 16 |
ERRATA_FW4000 4096
|
| 17 |
ERRATA_RESETRAM 8192
|
| 18 |
]
|
| 19 |
"21 C:\Programmer\HI-TECH Software\PICC-18\9.50\include\pic18fxx2.h
|
| 20 |
[v _TOSU `VNuc 1 s 1 @4095 ]
|
| 21 |
"22
|
| 22 |
[v _TOSH `VNuc 1 s 1 @4094 ]
|
| 23 |
"23
|
| 24 |
[v _TOSL `VNuc 1 s 1 @4093 ]
|
| 25 |
"24
|
| 26 |
[v _STKPTR `VNuc 1 s 1 @4092 ]
|
| 27 |
"25
|
| 28 |
[v _PCLATU `VNuc 1 s 1 @4091 ]
|
| 29 |
"26
|
| 30 |
[v _PCLATH `VNuc 1 s 1 @4090 ]
|
| 31 |
"27
|
| 32 |
[v _PCL `VNuc 1 s 1 @4089 ]
|
| 33 |
"28
|
| 34 |
[v _TBLPTR `*VFuc 1 s 2 @4086 ]
|
| 35 |
"29
|
| 36 |
[v _TBLPTRU `VNuc 1 s 1 @4088 ]
|
| 37 |
"30
|
| 38 |
[v _TBLPTRH `VNuc 1 s 1 @4087 ]
|
| 39 |
"31
|
| 40 |
[v _TBLPTRL `VNuc 1 s 1 @4086 ]
|
| 41 |
"32
|
| 42 |
[v _TABLAT `VNuc 1 s 1 @4085 ]
|
| 43 |
"33
|
| 44 |
[v _PRODH `VNuc 1 s 1 @4084 ]
|
| 45 |
"34
|
| 46 |
[v _PRODL `VNuc 1 s 1 @4083 ]
|
| 47 |
"35
|
| 48 |
[v _INTCON `VNuc 1 s 1 @4082 ]
|
| 49 |
"36
|
| 50 |
[v _INTCON2 `Nuc 1 s 1 @4081 ]
|
| 51 |
"37
|
| 52 |
[v _INTCON3 `VNuc 1 s 1 @4080 ]
|
| 53 |
"38
|
| 54 |
[v _INDF0 `VNuc 1 s 1 @4079 ]
|
| 55 |
"39
|
| 56 |
[v _POSTINC0 `VNuc 1 s 1 @4078 ]
|
| 57 |
"40
|
| 58 |
[v _POSTDEC0 `VNuc 1 s 1 @4077 ]
|
| 59 |
"41
|
| 60 |
[v _PREINC0 `VNuc 1 s 1 @4076 ]
|
| 61 |
"42
|
| 62 |
[v _PLUSW0 `VNuc 1 s 1 @4075 ]
|
| 63 |
"43
|
| 64 |
[v _FSR0H `VNuc 1 s 1 @4074 ]
|
| 65 |
"44
|
| 66 |
[v _FSR0L `VNuc 1 s 1 @4073 ]
|
| 67 |
"45
|
| 68 |
[v _WREG `VNuc 1 s 1 @4072 ]
|
| 69 |
"46
|
| 70 |
[v _INDF1 `VNuc 1 s 1 @4071 ]
|
| 71 |
"47
|
| 72 |
[v _POSTINC1 `VNuc 1 s 1 @4070 ]
|
| 73 |
"48
|
| 74 |
[v _POSTDEC1 `VNuc 1 s 1 @4069 ]
|
| 75 |
"49
|
| 76 |
[v _PREINC1 `VNuc 1 s 1 @4068 ]
|
| 77 |
"50
|
| 78 |
[v _PLUSW1 `VNuc 1 s 1 @4067 ]
|
| 79 |
"51
|
| 80 |
[v _FSR1H `VNuc 1 s 1 @4066 ]
|
| 81 |
"52
|
| 82 |
[v _FSR1L `VNuc 1 s 1 @4065 ]
|
| 83 |
"53
|
| 84 |
[v _BSR `Nuc 1 s 1 @4064 ]
|
| 85 |
"54
|
| 86 |
[v _INDF2 `VNuc 1 s 1 @4063 ]
|
| 87 |
"55
|
| 88 |
[v _POSTINC2 `VNuc 1 s 1 @4062 ]
|
| 89 |
"56
|
| 90 |
[v _POSTDEC2 `VNuc 1 s 1 @4061 ]
|
| 91 |
"57
|
| 92 |
[v _PREINC2 `VNuc 1 s 1 @4060 ]
|
| 93 |
"58
|
| 94 |
[v _PLUSW2 `VNuc 1 s 1 @4059 ]
|
| 95 |
"59
|
| 96 |
[v _FSR2H `VNuc 1 s 1 @4058 ]
|
| 97 |
"60
|
| 98 |
[v _FSR2L `VNuc 1 s 1 @4057 ]
|
| 99 |
"61
|
| 100 |
[v _STATUS `VNuc 1 s 1 @4056 ]
|
| 101 |
"62
|
| 102 |
[v _TMR0 `VNui 1 s 2 @4054 ]
|
| 103 |
"63
|
| 104 |
[v _TMR0H `VNuc 1 s 1 @4055 ]
|
| 105 |
"64
|
| 106 |
[v _TMR0L `VNuc 1 s 1 @4054 ]
|
| 107 |
"65
|
| 108 |
[v _T0CON `Nuc 1 s 1 @4053 ]
|
| 109 |
"66
|
| 110 |
[v _OSCCON `VNuc 1 s 1 @4051 ]
|
| 111 |
"67
|
| 112 |
[v _LVDCON `VNuc 1 s 1 @4050 ]
|
| 113 |
"68
|
| 114 |
[v _WDTCON `Nuc 1 s 1 @4049 ]
|
| 115 |
"69
|
| 116 |
[v _RCON `VNuc 1 s 1 @4048 ]
|
| 117 |
"70
|
| 118 |
[v _TMR1 `VNui 1 s 2 @4046 ]
|
| 119 |
"71
|
| 120 |
[v _TMR1H `VNuc 1 s 1 @4047 ]
|
| 121 |
"72
|
| 122 |
[v _TMR1L `VNuc 1 s 1 @4046 ]
|
| 123 |
"73
|
| 124 |
[v _T1CON `Nuc 1 s 1 @4045 ]
|
| 125 |
"74
|
| 126 |
[v _TMR2 `VNuc 1 s 1 @4044 ]
|
| 127 |
"75
|
| 128 |
[v _PR2 `VNuc 1 s 1 @4043 ]
|
| 129 |
"76
|
| 130 |
[v _T2CON `Nuc 1 s 1 @4042 ]
|
| 131 |
"77
|
| 132 |
[v _SSPBUF `VNuc 1 s 1 @4041 ]
|
| 133 |
"78
|
| 134 |
[v _SSPADD `VNuc 1 s 1 @4040 ]
|
| 135 |
"79
|
| 136 |
[v _SSPSTAT `VNuc 1 s 1 @4039 ]
|
| 137 |
"80
|
| 138 |
[v _SSPCON1 `VNuc 1 s 1 @4038 ]
|
| 139 |
"81
|
| 140 |
[v _SSPCON2 `VNuc 1 s 1 @4037 ]
|
| 141 |
"82
|
| 142 |
[v _ADRES `VNui 1 s 2 @4035 ]
|
| 143 |
"83
|
| 144 |
[v _ADRESH `VNuc 1 s 1 @4036 ]
|
| 145 |
"84
|
| 146 |
[v _ADRESL `VNuc 1 s 1 @4035 ]
|
| 147 |
"85
|
| 148 |
[v _ADCON0 `VNuc 1 s 1 @4034 ]
|
| 149 |
"86
|
| 150 |
[v _ADCON1 `Nuc 1 s 1 @4033 ]
|
| 151 |
"87
|
| 152 |
[v _CCPR1 `VNui 1 s 2 @4030 ]
|
| 153 |
"88
|
| 154 |
[v _CCPR1H `VNuc 1 s 1 @4031 ]
|
| 155 |
"89
|
| 156 |
[v _CCPR1L `VNuc 1 s 1 @4030 ]
|
| 157 |
"90
|
| 158 |
[v _CCP1CON `VNuc 1 s 1 @4029 ]
|
| 159 |
"91
|
| 160 |
[v _CCPR2 `VNui 1 s 2 @4027 ]
|
| 161 |
"92
|
| 162 |
[v _CCPR2H `VNuc 1 s 1 @4028 ]
|
| 163 |
"93
|
| 164 |
[v _CCPR2L `VNuc 1 s 1 @4027 ]
|
| 165 |
"94
|
| 166 |
[v _CCP2CON `VNuc 1 s 1 @4026 ]
|
| 167 |
"95
|
| 168 |
[v _TMR3 `VNui 1 s 2 @4018 ]
|
| 169 |
"96
|
| 170 |
[v _TMR3H `VNuc 1 s 1 @4019 ]
|
| 171 |
"97
|
| 172 |
[v _TMR3L `VNuc 1 s 1 @4018 ]
|
| 173 |
"98
|
| 174 |
[v _T3CON `Nuc 1 s 1 @4017 ]
|
| 175 |
"99
|
| 176 |
[v _SPBRG `Nuc 1 s 1 @4015 ]
|
| 177 |
"100
|
| 178 |
[v _RCREG `VNuc 1 s 1 @4014 ]
|
| 179 |
"101
|
| 180 |
[v _TXREG `VNuc 1 s 1 @4013 ]
|
| 181 |
"102
|
| 182 |
[v _TXSTA `VNuc 1 s 1 @4012 ]
|
| 183 |
"103
|
| 184 |
[v _RCSTA `VNuc 1 s 1 @4011 ]
|
| 185 |
"104
|
| 186 |
[v _EEADR `VNuc 1 s 1 @4009 ]
|
| 187 |
"105
|
| 188 |
[v _EEDATA `VNuc 1 s 1 @4008 ]
|
| 189 |
"106
|
| 190 |
[v _EECON2 `VNuc 1 s 1 @4007 ]
|
| 191 |
"107
|
| 192 |
[v _EECON1 `VNuc 1 s 1 @4006 ]
|
| 193 |
"108
|
| 194 |
[v _IPR2 `Nuc 1 s 1 @4002 ]
|
| 195 |
"109
|
| 196 |
[v _PIR2 `VNuc 1 s 1 @4001 ]
|
| 197 |
"110
|
| 198 |
[v _PIE2 `Nuc 1 s 1 @4000 ]
|
| 199 |
"111
|
| 200 |
[v _IPR1 `Nuc 1 s 1 @3999 ]
|
| 201 |
"112
|
| 202 |
[v _PIR1 `VNuc 1 s 1 @3998 ]
|
| 203 |
"113
|
| 204 |
[v _PIE1 `Nuc 1 s 1 @3997 ]
|
| 205 |
"114
|
| 206 |
[v _TRISC `VNuc 1 s 1 @3988 ]
|
| 207 |
"115
|
| 208 |
[v _TRISB `VNuc 1 s 1 @3987 ]
|
| 209 |
"116
|
| 210 |
[v _TRISA `VNuc 1 s 1 @3986 ]
|
| 211 |
"117
|
| 212 |
[v _LATC `VNuc 1 s 1 @3979 ]
|
| 213 |
"118
|
| 214 |
[v _LATB `VNuc 1 s 1 @3978 ]
|
| 215 |
"119
|
| 216 |
[v _LATA `VNuc 1 s 1 @3977 ]
|
| 217 |
"120
|
| 218 |
[v _PORTC `VNuc 1 s 1 @3970 ]
|
| 219 |
"121
|
| 220 |
[v _PORTB `VNuc 1 s 1 @3969 ]
|
| 221 |
"122
|
| 222 |
[v _PORTA `VNuc 1 s 1 @3968 ]
|
| 223 |
"124
|
| 224 |
[v _TRISE `VNuc 1 s 1 @3990 ]
|
| 225 |
"125
|
| 226 |
[v _TRISD `VNuc 1 s 1 @3989 ]
|
| 227 |
"126
|
| 228 |
[v _LATE `VNuc 1 s 1 @3981 ]
|
| 229 |
"127
|
| 230 |
[v _LATD `VNuc 1 s 1 @3980 ]
|
| 231 |
"128
|
| 232 |
[v _PORTE `VNuc 1 s 1 @3972 ]
|
| 233 |
"129
|
| 234 |
[v _PORTD `VNuc 1 s 1 @3971 ]
|
| 235 |
"134
|
| 236 |
[v _NEGATIVE `VNb 1 s 0 @32452 ]
|
| 237 |
"135
|
| 238 |
[v _OVERFLOW `VNb 1 s 0 @32451 ]
|
| 239 |
"136
|
| 240 |
[v _ZERO `VNb 1 s 0 @32450 ]
|
| 241 |
"137
|
| 242 |
[v _DC `VNb 1 s 0 @32449 ]
|
| 243 |
"138
|
| 244 |
[v _CARRY `VNb 1 s 0 @32448 ]
|
| 245 |
"141
|
| 246 |
[v _STKFUL `VNb 1 s 0 @32743 ]
|
| 247 |
"142
|
| 248 |
[v _STKUNF `VNb 1 s 0 @32742 ]
|
| 249 |
"143
|
| 250 |
[v _SP4 `VNb 1 s 0 @32740 ]
|
| 251 |
"144
|
| 252 |
[v _SP3 `VNb 1 s 0 @32739 ]
|
| 253 |
"145
|
| 254 |
[v _SP2 `VNb 1 s 0 @32738 ]
|
| 255 |
"146
|
| 256 |
[v _SP1 `VNb 1 s 0 @32737 ]
|
| 257 |
"147
|
| 258 |
[v _SP0 `VNb 1 s 0 @32736 ]
|
| 259 |
"150
|
| 260 |
[v _GIE `Nb 1 s 0 @32663 ]
|
| 261 |
"151
|
| 262 |
[v _GIEH `Nb 1 s 0 @32663 ]
|
| 263 |
"152
|
| 264 |
[v _PEIE `Nb 1 s 0 @32662 ]
|
| 265 |
"153
|
| 266 |
[v _GIEL `Nb 1 s 0 @32662 ]
|
| 267 |
"154
|
| 268 |
[v _TMR0IE `Nb 1 s 0 @32661 ]
|
| 269 |
"155
|
| 270 |
[v _INT0IE `Nb 1 s 0 @32660 ]
|
| 271 |
"156
|
| 272 |
[v _RBIE `Nb 1 s 0 @32659 ]
|
| 273 |
"157
|
| 274 |
[v _TMR0IF `VNb 1 s 0 @32658 ]
|
| 275 |
"158
|
| 276 |
[v _INT0IF `VNb 1 s 0 @32657 ]
|
| 277 |
"159
|
| 278 |
[v _RBIF `VNb 1 s 0 @32656 ]
|
| 279 |
"160
|
| 280 |
[v _T0IF `VNb 1 s 0 @32658 ]
|
| 281 |
"163
|
| 282 |
[v _RBPU `Nb 1 s 0 @32655 ]
|
| 283 |
"164
|
| 284 |
[v _INTEDG0 `Nb 1 s 0 @32654 ]
|
| 285 |
"165
|
| 286 |
[v _INTEDG1 `Nb 1 s 0 @32653 ]
|
| 287 |
"166
|
| 288 |
[v _INTEDG2 `Nb 1 s 0 @32652 ]
|
| 289 |
"167
|
| 290 |
[v _TMR0IP `Nb 1 s 0 @32650 ]
|
| 291 |
"168
|
| 292 |
[v _RBIP `Nb 1 s 0 @32648 ]
|
| 293 |
"169
|
| 294 |
[v _T0IP `Nb 1 s 0 @32650 ]
|
| 295 |
"172
|
| 296 |
[v _INT2IP `Nb 1 s 0 @32647 ]
|
| 297 |
"173
|
| 298 |
[v _INT1IP `Nb 1 s 0 @32646 ]
|
| 299 |
"174
|
| 300 |
[v _INT2IE `Nb 1 s 0 @32644 ]
|
| 301 |
"175
|
| 302 |
[v _INT1IE `Nb 1 s 0 @32643 ]
|
| 303 |
"176
|
| 304 |
[v _INT2IF `VNb 1 s 0 @32641 ]
|
| 305 |
"177
|
| 306 |
[v _INT1IF `VNb 1 s 0 @32640 ]
|
| 307 |
"180
|
| 308 |
[v _TMR0ON `Nb 1 s 0 @32431 ]
|
| 309 |
"181
|
| 310 |
[v _T08BIT `Nb 1 s 0 @32430 ]
|
| 311 |
"182
|
| 312 |
[v _T0CS `Nb 1 s 0 @32429 ]
|
| 313 |
"183
|
| 314 |
[v _T0SE `Nb 1 s 0 @32428 ]
|
| 315 |
"184
|
| 316 |
[v _PSA `Nb 1 s 0 @32427 ]
|
| 317 |
"185
|
| 318 |
[v _T0PS2 `Nb 1 s 0 @32426 ]
|
| 319 |
"186
|
| 320 |
[v _T0PS1 `Nb 1 s 0 @32425 ]
|
| 321 |
"187
|
| 322 |
[v _T0PS0 `Nb 1 s 0 @32424 ]
|
| 323 |
"190
|
| 324 |
[v _SCS `Nb 1 s 0 @32408 ]
|
| 325 |
"193
|
| 326 |
[v _IRVST `VNb 1 s 0 @32405 ]
|
| 327 |
"194
|
| 328 |
[v _LVDEN `Nb 1 s 0 @32404 ]
|
| 329 |
"195
|
| 330 |
[v _LVDL3 `Nb 1 s 0 @32403 ]
|
| 331 |
"196
|
| 332 |
[v _LVDL2 `Nb 1 s 0 @32402 ]
|
| 333 |
"197
|
| 334 |
[v _LVDL1 `Nb 1 s 0 @32401 ]
|
| 335 |
"198
|
| 336 |
[v _LVDL0 `Nb 1 s 0 @32400 ]
|
| 337 |
"201
|
| 338 |
[v _SWDTEN `Nb 1 s 0 @32392 ]
|
| 339 |
"204
|
| 340 |
[v _IPEN `Nb 1 s 0 @32391 ]
|
| 341 |
"205
|
| 342 |
[v _RI `VNb 1 s 0 @32388 ]
|
| 343 |
"206
|
| 344 |
[v _TO `VNb 1 s 0 @32387 ]
|
| 345 |
"207
|
| 346 |
[v _PD `VNb 1 s 0 @32386 ]
|
| 347 |
"208
|
| 348 |
[v _POR `VNb 1 s 0 @32385 ]
|
| 349 |
"209
|
| 350 |
[v _BOR `VNb 1 s 0 @32384 ]
|
| 351 |
"212
|
| 352 |
[v _RD16 `Nb 1 s 0 @32367 ]
|
| 353 |
"213
|
| 354 |
[v _T1RD16 `Nb 1 s 0 @32367 ]
|
| 355 |
"214
|
| 356 |
[v _T1CKPS1 `Nb 1 s 0 @32365 ]
|
| 357 |
"215
|
| 358 |
[v _T1CKPS0 `Nb 1 s 0 @32364 ]
|
| 359 |
"216
|
| 360 |
[v _T1OSCEN `Nb 1 s 0 @32363 ]
|
| 361 |
"217
|
| 362 |
[v _T1SYNC `Nb 1 s 0 @32362 ]
|
| 363 |
"218
|
| 364 |
[v _TMR1CS `Nb 1 s 0 @32361 ]
|
| 365 |
"219
|
| 366 |
[v _TMR1ON `Nb 1 s 0 @32360 ]
|
| 367 |
"222
|
| 368 |
[v _TOUTPS3 `Nb 1 s 0 @32342 ]
|
| 369 |
"223
|
| 370 |
[v _TOUTPS2 `Nb 1 s 0 @32341 ]
|
| 371 |
"224
|
| 372 |
[v _TOUTPS1 `Nb 1 s 0 @32340 ]
|
| 373 |
"225
|
| 374 |
[v _TOUTPS0 `Nb 1 s 0 @32339 ]
|
| 375 |
"226
|
| 376 |
[v _TMR2ON `Nb 1 s 0 @32338 ]
|
| 377 |
"227
|
| 378 |
[v _T2CKPS1 `Nb 1 s 0 @32337 ]
|
| 379 |
"228
|
| 380 |
[v _T2CKPS0 `Nb 1 s 0 @32336 ]
|
| 381 |
"231
|
| 382 |
[v _SMP `Nb 1 s 0 @32319 ]
|
| 383 |
"232
|
| 384 |
[v _CKE `Nb 1 s 0 @32318 ]
|
| 385 |
"233
|
| 386 |
[v _DA `VNb 1 s 0 @32317 ]
|
| 387 |
"234
|
| 388 |
[v _P `VNb 1 s 0 @32316 ]
|
| 389 |
"235
|
| 390 |
[v _S `VNb 1 s 0 @32315 ]
|
| 391 |
"236
|
| 392 |
[v _RW `VNb 1 s 0 @32314 ]
|
| 393 |
"237
|
| 394 |
[v _UA `VNb 1 s 0 @32313 ]
|
| 395 |
"238
|
| 396 |
[v _BF `VNb 1 s 0 @32312 ]
|
| 397 |
"240
|
| 398 |
[v _STOP `VNb 1 s 0 @32316 ]
|
| 399 |
"241
|
| 400 |
[v _START `VNb 1 s 0 @32315 ]
|
| 401 |
"244
|
| 402 |
[v _WCOL `VNb 1 s 0 @32311 ]
|
| 403 |
"245
|
| 404 |
[v _SSPOV `VNb 1 s 0 @32310 ]
|
| 405 |
"246
|
| 406 |
[v _SSPEN `Nb 1 s 0 @32309 ]
|
| 407 |
"247
|
| 408 |
[v _CKP `Nb 1 s 0 @32308 ]
|
| 409 |
"248
|
| 410 |
[v _SSPM3 `Nb 1 s 0 @32307 ]
|
| 411 |
"249
|
| 412 |
[v _SSPM2 `Nb 1 s 0 @32306 ]
|
| 413 |
"250
|
| 414 |
[v _SSPM1 `Nb 1 s 0 @32305 ]
|
| 415 |
"251
|
| 416 |
[v _SSPM0 `Nb 1 s 0 @32304 ]
|
| 417 |
"254
|
| 418 |
[v _GCEN `Nb 1 s 0 @32303 ]
|
| 419 |
"255
|
| 420 |
[v _ACKSTAT `VNb 1 s 0 @32302 ]
|
| 421 |
"256
|
| 422 |
[v _ACKDT `VNb 1 s 0 @32301 ]
|
| 423 |
"257
|
| 424 |
[v _ACKEN `VNb 1 s 0 @32300 ]
|
| 425 |
"258
|
| 426 |
[v _RCEN `Nb 1 s 0 @32299 ]
|
| 427 |
"259
|
| 428 |
[v _PEN `VNb 1 s 0 @32298 ]
|
| 429 |
"260
|
| 430 |
[v _RSEN `VNb 1 s 0 @32297 ]
|
| 431 |
"261
|
| 432 |
[v _SEN `VNb 1 s 0 @32296 ]
|
| 433 |
"264
|
| 434 |
[v _ADCS1 `Nb 1 s 0 @32279 ]
|
| 435 |
"265
|
| 436 |
[v _ADCS0 `Nb 1 s 0 @32278 ]
|
| 437 |
"266
|
| 438 |
[v _CHS2 `Nb 1 s 0 @32277 ]
|
| 439 |
"267
|
| 440 |
[v _CHS1 `Nb 1 s 0 @32276 ]
|
| 441 |
"268
|
| 442 |
[v _CHS0 `Nb 1 s 0 @32275 ]
|
| 443 |
"269
|
| 444 |
[v _GODONE `VNb 1 s 0 @32274 ]
|
| 445 |
"270
|
| 446 |
[v _ADON `Nb 1 s 0 @32272 ]
|
| 447 |
"273
|
| 448 |
[v _ADFM `Nb 1 s 0 @32271 ]
|
| 449 |
"274
|
| 450 |
[v _ADCS2 `Nb 1 s 0 @32270 ]
|
| 451 |
"275
|
| 452 |
[v _PCFG3 `Nb 1 s 0 @32267 ]
|
| 453 |
"276
|
| 454 |
[v _PCFG2 `Nb 1 s 0 @32266 ]
|
| 455 |
"277
|
| 456 |
[v _PCFG1 `Nb 1 s 0 @32265 ]
|
| 457 |
"278
|
| 458 |
[v _PCFG0 `Nb 1 s 0 @32264 ]
|
| 459 |
"281
|
| 460 |
[v _DC1B1 `VNb 1 s 0 @32237 ]
|
| 461 |
"282
|
| 462 |
[v _DC1B0 `VNb 1 s 0 @32236 ]
|
| 463 |
"283
|
| 464 |
[v _CCP1M3 `Nb 1 s 0 @32235 ]
|
| 465 |
"284
|
| 466 |
[v _CCP1M2 `Nb 1 s 0 @32234 ]
|
| 467 |
"285
|
| 468 |
[v _CCP1M1 `Nb 1 s 0 @32233 ]
|
| 469 |
"286
|
| 470 |
[v _CCP1M0 `Nb 1 s 0 @32232 ]
|
| 471 |
"289
|
| 472 |
[v _DC2B1 `VNb 1 s 0 @32213 ]
|
| 473 |
"290
|
| 474 |
[v _DC2B0 `VNb 1 s 0 @32212 ]
|
| 475 |
"291
|
| 476 |
[v _CCP2M3 `Nb 1 s 0 @32211 ]
|
| 477 |
"292
|
| 478 |
[v _CCP2M2 `Nb 1 s 0 @32210 ]
|
| 479 |
"293
|
| 480 |
[v _CCP2M1 `Nb 1 s 0 @32209 ]
|
| 481 |
"294
|
| 482 |
[v _CCP2M0 `Nb 1 s 0 @32208 ]
|
| 483 |
"297
|
| 484 |
[v _T3RD16 `Nb 1 s 0 @32143 ]
|
| 485 |
"298
|
| 486 |
[v _T3CCP2 `Nb 1 s 0 @32142 ]
|
| 487 |
"299
|
| 488 |
[v _T3CKPS1 `Nb 1 s 0 @32141 ]
|
| 489 |
"300
|
| 490 |
[v _T3CKPS0 `Nb 1 s 0 @32140 ]
|
| 491 |
"301
|
| 492 |
[v _T3CCP1 `Nb 1 s 0 @32139 ]
|
| 493 |
"302
|
| 494 |
[v _T3SYNC `Nb 1 s 0 @32138 ]
|
| 495 |
"303
|
| 496 |
[v _TMR3CS `Nb 1 s 0 @32137 ]
|
| 497 |
"304
|
| 498 |
[v _TMR3ON `Nb 1 s 0 @32136 ]
|
| 499 |
"307
|
| 500 |
[v _CSRC `Nb 1 s 0 @32103 ]
|
| 501 |
"308
|
| 502 |
[v _TX9 `Nb 1 s 0 @32102 ]
|
| 503 |
"309
|
| 504 |
[v _TXEN `Nb 1 s 0 @32101 ]
|
| 505 |
"310
|
| 506 |
[v _SYNC `Nb 1 s 0 @32100 ]
|
| 507 |
"311
|
| 508 |
[v _BRGH `Nb 1 s 0 @32098 ]
|
| 509 |
"312
|
| 510 |
[v _TRMT `VNb 1 s 0 @32097 ]
|
| 511 |
"313
|
| 512 |
[v _TX9D `Nb 1 s 0 @32096 ]
|
| 513 |
"316
|
| 514 |
[v _SPEN `Nb 1 s 0 @32095 ]
|
| 515 |
"317
|
| 516 |
[v _RX9 `Nb 1 s 0 @32094 ]
|
| 517 |
"318
|
| 518 |
[v _SREN `Nb 1 s 0 @32093 ]
|
| 519 |
"319
|
| 520 |
[v _CREN `Nb 1 s 0 @32092 ]
|
| 521 |
"320
|
| 522 |
[v _ADDEN `Nb 1 s 0 @32091 ]
|
| 523 |
"321
|
| 524 |
[v _FERR `VNb 1 s 0 @32090 ]
|
| 525 |
"322
|
| 526 |
[v _OERR `VNb 1 s 0 @32089 ]
|
| 527 |
"323
|
| 528 |
[v _RX9D `VNb 1 s 0 @32088 ]
|
| 529 |
"326
|
| 530 |
[v _EEPGD `Nb 1 s 0 @32055 ]
|
| 531 |
"327
|
| 532 |
[v _CFGS `Nb 1 s 0 @32054 ]
|
| 533 |
"329
|
| 534 |
[v _EEFS `Nb 1 s 0 @32054 ]
|
| 535 |
"330
|
| 536 |
[v _FREE `VNb 1 s 0 @32052 ]
|
| 537 |
"331
|
| 538 |
[v _WRERR `VNb 1 s 0 @32051 ]
|
| 539 |
"332
|
| 540 |
[v _WREN `VNb 1 s 0 @32050 ]
|
| 541 |
"333
|
| 542 |
[v _WR `VNb 1 s 0 @32049 ]
|
| 543 |
"334
|
| 544 |
[v _RD `VNb 1 s 0 @32048 ]
|
| 545 |
"337
|
| 546 |
[v _EEIP `Nb 1 s 0 @32020 ]
|
| 547 |
"338
|
| 548 |
[v _BCLIP `Nb 1 s 0 @32019 ]
|
| 549 |
"339
|
| 550 |
[v _LVDIP `Nb 1 s 0 @32018 ]
|
| 551 |
"340
|
| 552 |
[v _TMR3IP `Nb 1 s 0 @32017 ]
|
| 553 |
"341
|
| 554 |
[v _CCP2IP `Nb 1 s 0 @32016 ]
|
| 555 |
"344
|
| 556 |
[v _EEIF `VNb 1 s 0 @32012 ]
|
| 557 |
"345
|
| 558 |
[v _BCLIF `VNb 1 s 0 @32011 ]
|
| 559 |
"346
|
| 560 |
[v _LVDIF `VNb 1 s 0 @32010 ]
|
| 561 |
"347
|
| 562 |
[v _TMR3IF `VNb 1 s 0 @32009 ]
|
| 563 |
"348
|
| 564 |
[v _CCP2IF `VNb 1 s 0 @32008 ]
|
| 565 |
"351
|
| 566 |
[v _EEIE `Nb 1 s 0 @32004 ]
|
| 567 |
"352
|
| 568 |
[v _BCLIE `Nb 1 s 0 @32003 ]
|
| 569 |
"353
|
| 570 |
[v _LVDIE `Nb 1 s 0 @32002 ]
|
| 571 |
"354
|
| 572 |
[v _TMR3IE `Nb 1 s 0 @32001 ]
|
| 573 |
"355
|
| 574 |
[v _CCP2IE `Nb 1 s 0 @32000 ]
|
| 575 |
"358
|
| 576 |
[v _PSPIP `Nb 1 s 0 @31999 ]
|
| 577 |
"359
|
| 578 |
[v _ADIP `Nb 1 s 0 @31998 ]
|
| 579 |
"360
|
| 580 |
[v _RCIP `Nb 1 s 0 @31997 ]
|
| 581 |
"361
|
| 582 |
[v _TXIP `Nb 1 s 0 @31996 ]
|
| 583 |
"362
|
| 584 |
[v _SSPIP `Nb 1 s 0 @31995 ]
|
| 585 |
"363
|
| 586 |
[v _CCP1IP `Nb 1 s 0 @31994 ]
|
| 587 |
"364
|
| 588 |
[v _TMR2IP `Nb 1 s 0 @31993 ]
|
| 589 |
"365
|
| 590 |
[v _TMR1IP `Nb 1 s 0 @31992 ]
|
| 591 |
"368
|
| 592 |
[v _PSPIF `VNb 1 s 0 @31991 ]
|
| 593 |
"369
|
| 594 |
[v _ADIF `VNb 1 s 0 @31990 ]
|
| 595 |
"370
|
| 596 |
[v _RCIF `VNb 1 s 0 @31989 ]
|
| 597 |
"371
|
| 598 |
[v _TXIF `VNb 1 s 0 @31988 ]
|
| 599 |
"372
|
| 600 |
[v _SSPIF `VNb 1 s 0 @31987 ]
|
| 601 |
"373
|
| 602 |
[v _CCP1IF `VNb 1 s 0 @31986 ]
|
| 603 |
"374
|
| 604 |
[v _TMR2IF `VNb 1 s 0 @31985 ]
|
| 605 |
"375
|
| 606 |
[v _TMR1IF `VNb 1 s 0 @31984 ]
|
| 607 |
"378
|
| 608 |
[v _PSPIE `Nb 1 s 0 @31983 ]
|
| 609 |
"379
|
| 610 |
[v _ADIE `Nb 1 s 0 @31982 ]
|
| 611 |
"380
|
| 612 |
[v _RCIE `Nb 1 s 0 @31981 ]
|
| 613 |
"381
|
| 614 |
[v _TXIE `Nb 1 s 0 @31980 ]
|
| 615 |
"382
|
| 616 |
[v _SSPIE `Nb 1 s 0 @31979 ]
|
| 617 |
"383
|
| 618 |
[v _CCP1IE `Nb 1 s 0 @31978 ]
|
| 619 |
"384
|
| 620 |
[v _TMR2IE `Nb 1 s 0 @31977 ]
|
| 621 |
"385
|
| 622 |
[v _TMR1IE `Nb 1 s 0 @31976 ]
|
| 623 |
"389
|
| 624 |
[v _IBF `VNb 1 s 0 @31927 ]
|
| 625 |
"390
|
| 626 |
[v _OBF `VNb 1 s 0 @31926 ]
|
| 627 |
"391
|
| 628 |
[v _IBOV `VNb 1 s 0 @31925 ]
|
| 629 |
"392
|
| 630 |
[v _PSPMODE `VNb 1 s 0 @31924 ]
|
| 631 |
"393
|
| 632 |
[v _TRISE2 `VNb 1 s 0 @31922 ]
|
| 633 |
"394
|
| 634 |
[v _TRISE1 `VNb 1 s 0 @31921 ]
|
| 635 |
"395
|
| 636 |
[v _TRISE0 `VNb 1 s 0 @31920 ]
|
| 637 |
"398
|
| 638 |
[v _TRISD7 `VNb 1 s 0 @31919 ]
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| 639 |
"399
|
| 640 |
[v _TRISD6 `VNb 1 s 0 @31918 ]
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| 641 |
"400
|
| 642 |
[v _TRISD5 `VNb 1 s 0 @31917 ]
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| 643 |
"401
|
| 644 |
[v _TRISD4 `VNb 1 s 0 @31916 ]
|
| 645 |
"402
|
| 646 |
[v _TRISD3 `VNb 1 s 0 @31915 ]
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| 647 |
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|
| 648 |
[v _TRISD2 `VNb 1 s 0 @31914 ]
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| 649 |
"404
|
| 650 |
[v _TRISD1 `VNb 1 s 0 @31913 ]
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| 651 |
"405
|
| 652 |
[v _TRISD0 `VNb 1 s 0 @31912 ]
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| 653 |
"409
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| 654 |
[v _TRISC7 `VNb 1 s 0 @31911 ]
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| 655 |
"410
|
| 656 |
[v _TRISC6 `VNb 1 s 0 @31910 ]
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| 657 |
"411
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| 658 |
[v _TRISC5 `VNb 1 s 0 @31909 ]
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| 659 |
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|
| 660 |
[v _TRISC4 `VNb 1 s 0 @31908 ]
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| 661 |
"413
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| 662 |
[v _TRISC3 `VNb 1 s 0 @31907 ]
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| 663 |
"414
|
| 664 |
[v _TRISC2 `VNb 1 s 0 @31906 ]
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| 665 |
"415
|
| 666 |
[v _TRISC1 `VNb 1 s 0 @31905 ]
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| 667 |
"416
|
| 668 |
[v _TRISC0 `VNb 1 s 0 @31904 ]
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| 669 |
"419
|
| 670 |
[v _TRISB7 `VNb 1 s 0 @31903 ]
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| 671 |
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|
| 672 |
[v _TRISB6 `VNb 1 s 0 @31902 ]
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| 673 |
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| 674 |
[v _TRISB5 `VNb 1 s 0 @31901 ]
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| 675 |
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| 676 |
[v _TRISB4 `VNb 1 s 0 @31900 ]
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| 677 |
"423
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| 678 |
[v _TRISB3 `VNb 1 s 0 @31899 ]
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| 679 |
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| 680 |
[v _TRISB2 `VNb 1 s 0 @31898 ]
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| 681 |
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| 682 |
[v _TRISB1 `VNb 1 s 0 @31897 ]
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| 683 |
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| 684 |
[v _TRISB0 `VNb 1 s 0 @31896 ]
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| 685 |
"429
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| 686 |
[v _TRISA6 `VNb 1 s 0 @31894 ]
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| 687 |
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| 688 |
[v _TRISA5 `VNb 1 s 0 @31893 ]
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| 689 |
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| 690 |
[v _TRISA4 `VNb 1 s 0 @31892 ]
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| 691 |
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|
| 692 |
[v _TRISA3 `VNb 1 s 0 @31891 ]
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| 693 |
"433
|
| 694 |
[v _TRISA2 `VNb 1 s 0 @31890 ]
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| 695 |
"434
|
| 696 |
[v _TRISA1 `VNb 1 s 0 @31889 ]
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| 697 |
"435
|
| 698 |
[v _TRISA0 `VNb 1 s 0 @31888 ]
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| 699 |
"439
|
| 700 |
[v _LE0 `VNb 1 s 0 @31848 ]
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| 701 |
"440
|
| 702 |
[v _LE1 `VNb 1 s 0 @31849 ]
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| 703 |
"441
|
| 704 |
[v _LE2 `VNb 1 s 0 @31850 ]
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| 705 |
"443
|
| 706 |
[v _LATE0 `VNb 1 s 0 @31848 ]
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| 707 |
"444
|
| 708 |
[v _LATE1 `VNb 1 s 0 @31849 ]
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| 709 |
"445
|
| 710 |
[v _LATE2 `VNb 1 s 0 @31850 ]
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| 711 |
"448
|
| 712 |
[v _LD0 `VNb 1 s 0 @31840 ]
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| 713 |
"449
|
| 714 |
[v _LD1 `VNb 1 s 0 @31841 ]
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| 715 |
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|
| 716 |
[v _LD2 `VNb 1 s 0 @31842 ]
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| 717 |
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| 718 |
[v _LD3 `VNb 1 s 0 @31843 ]
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| 719 |
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| 720 |
[v _LD4 `VNb 1 s 0 @31844 ]
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| 721 |
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|
| 722 |
[v _LD5 `VNb 1 s 0 @31845 ]
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| 723 |
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|
| 724 |
[v _LD6 `VNb 1 s 0 @31846 ]
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| 725 |
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|
| 726 |
[v _LD7 `VNb 1 s 0 @31847 ]
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| 727 |
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| 728 |
[v _LATD0 `VNb 1 s 0 @31840 ]
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| 729 |
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| 730 |
[v _LATD1 `VNb 1 s 0 @31841 ]
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| 731 |
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| 732 |
[v _LATD2 `VNb 1 s 0 @31842 ]
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| 733 |
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| 734 |
[v _LATD3 `VNb 1 s 0 @31843 ]
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| 735 |
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| 736 |
[v _LATD4 `VNb 1 s 0 @31844 ]
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| 737 |
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| 738 |
[v _LATD5 `VNb 1 s 0 @31845 ]
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| 739 |
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| 740 |
[v _LATD6 `VNb 1 s 0 @31846 ]
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| 741 |
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| 742 |
[v _LATD7 `VNb 1 s 0 @31847 ]
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| 743 |
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| 744 |
[v _LC0 `VNb 1 s 0 @31832 ]
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| 745 |
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| 746 |
[v _LC1 `VNb 1 s 0 @31833 ]
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| 747 |
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| 748 |
[v _LC2 `VNb 1 s 0 @31834 ]
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| 749 |
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| 750 |
[v _LC3 `VNb 1 s 0 @31835 ]
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| 751 |
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[v _LC4 `VNb 1 s 0 @31836 ]
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| 753 |
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| 754 |
[v _LC5 `VNb 1 s 0 @31837 ]
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| 755 |
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| 756 |
[v _LC6 `VNb 1 s 0 @31838 ]
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| 757 |
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| 758 |
[v _LC7 `VNb 1 s 0 @31839 ]
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| 759 |
"477
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| 760 |
[v _LATC0 `VNb 1 s 0 @31832 ]
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| 761 |
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| 762 |
[v _LATC1 `VNb 1 s 0 @31833 ]
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| 763 |
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| 764 |
[v _LATC2 `VNb 1 s 0 @31834 ]
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| 765 |
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| 766 |
[v _LATC3 `VNb 1 s 0 @31835 ]
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| 767 |
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| 768 |
[v _LATC4 `VNb 1 s 0 @31836 ]
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| 769 |
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| 770 |
[v _LATC5 `VNb 1 s 0 @31837 ]
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| 771 |
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| 772 |
[v _LATC6 `VNb 1 s 0 @31838 ]
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| 773 |
"484
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| 774 |
[v _LATC7 `VNb 1 s 0 @31839 ]
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| 775 |
"487
|
| 776 |
[v _LB0 `VNb 1 s 0 @31824 ]
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| 777 |
"488
|
| 778 |
[v _LB1 `VNb 1 s 0 @31825 ]
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| 779 |
"489
|
| 780 |
[v _LB2 `VNb 1 s 0 @31826 ]
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| 781 |
"490
|
| 782 |
[v _LB3 `VNb 1 s 0 @31827 ]
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| 783 |
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|
| 784 |
[v _LB4 `VNb 1 s 0 @31828 ]
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| 785 |
"492
|
| 786 |
[v _LB5 `VNb 1 s 0 @31829 ]
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| 787 |
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|
| 788 |
[v _LB6 `VNb 1 s 0 @31830 ]
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| 789 |
"494
|
| 790 |
[v _LB7 `VNb 1 s 0 @31831 ]
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| 791 |
"496
|
| 792 |
[v _LATB0 `VNb 1 s 0 @31824 ]
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| 793 |
"497
|
| 794 |
[v _LATB1 `VNb 1 s 0 @31825 ]
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| 795 |
"498
|
| 796 |
[v _LATB2 `VNb 1 s 0 @31826 ]
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| 797 |
"499
|
| 798 |
[v _LATB3 `VNb 1 s 0 @31827 ]
|
| 799 |
"500
|
| 800 |
[v _LATB4 `VNb 1 s 0 @31828 ]
|
| 801 |
"501
|
| 802 |
[v _LATB5 `VNb 1 s 0 @31829 ]
|
| 803 |
"502
|
| 804 |
[v _LATB6 `VNb 1 s 0 @31830 ]
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| 805 |
"503
|
| 806 |
[v _LATB7 `VNb 1 s 0 @31831 ]
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| 807 |
"506
|
| 808 |
[v _LA0 `VNb 1 s 0 @31816 ]
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| 809 |
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|
| 810 |
[v _LA1 `VNb 1 s 0 @31817 ]
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| 811 |
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|
| 812 |
[v _LA2 `VNb 1 s 0 @31818 ]
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| 813 |
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|
| 814 |
[v _LA3 `VNb 1 s 0 @31819 ]
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| 815 |
"510
|
| 816 |
[v _LA4 `VNb 1 s 0 @31820 ]
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| 817 |
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|
| 818 |
[v _LA5 `VNb 1 s 0 @31821 ]
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| 819 |
"512
|
| 820 |
[v _LA6 `VNb 1 s 0 @31822 ]
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| 821 |
"514
|
| 822 |
[v _LATA0 `VNb 1 s 0 @31816 ]
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| 823 |
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|
| 824 |
[v _LATA1 `VNb 1 s 0 @31817 ]
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| 825 |
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| 826 |
[v _LATA2 `VNb 1 s 0 @31818 ]
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| 827 |
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|
| 828 |
[v _LATA3 `VNb 1 s 0 @31819 ]
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| 829 |
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|
| 830 |
[v _LATA4 `VNb 1 s 0 @31820 ]
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| 831 |
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|
| 832 |
[v _LATA5 `VNb 1 s 0 @31821 ]
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| 833 |
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|
| 834 |
[v _LATA6 `VNb 1 s 0 @31822 ]
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| 835 |
"524
|
| 836 |
[v _RE0 `VNb 1 s 0 @31776 ]
|
| 837 |
"525
|
| 838 |
[v _RE1 `VNb 1 s 0 @31777 ]
|
| 839 |
"526
|
| 840 |
[v _RE2 `VNb 1 s 0 @31778 ]
|
| 841 |
"529
|
| 842 |
[v _RD0 `VNb 1 s 0 @31768 ]
|
| 843 |
"530
|
| 844 |
[v _RD1 `VNb 1 s 0 @31769 ]
|
| 845 |
"531
|
| 846 |
[v _RD2 `VNb 1 s 0 @31770 ]
|
| 847 |
"532
|
| 848 |
[v _RD3 `VNb 1 s 0 @31771 ]
|
| 849 |
"533
|
| 850 |
[v _RD4 `VNb 1 s 0 @31772 ]
|
| 851 |
"534
|
| 852 |
[v _RD5 `VNb 1 s 0 @31773 ]
|
| 853 |
"535
|
| 854 |
[v _RD6 `VNb 1 s 0 @31774 ]
|
| 855 |
"536
|
| 856 |
[v _RD7 `VNb 1 s 0 @31775 ]
|
| 857 |
"540
|
| 858 |
[v _RC0 `VNb 1 s 0 @31760 ]
|
| 859 |
"541
|
| 860 |
[v _RC1 `VNb 1 s 0 @31761 ]
|
| 861 |
"542
|
| 862 |
[v _RC2 `VNb 1 s 0 @31762 ]
|
| 863 |
"543
|
| 864 |
[v _RC3 `VNb 1 s 0 @31763 ]
|
| 865 |
"544
|
| 866 |
[v _RC4 `VNb 1 s 0 @31764 ]
|
| 867 |
"545
|
| 868 |
[v _RC5 `VNb 1 s 0 @31765 ]
|
| 869 |
"546
|
| 870 |
[v _RC6 `VNb 1 s 0 @31766 ]
|
| 871 |
"547
|
| 872 |
[v _RC7 `VNb 1 s 0 @31767 ]
|
| 873 |
"550
|
| 874 |
[v _RB0 `VNb 1 s 0 @31752 ]
|
| 875 |
"551
|
| 876 |
[v _RB1 `VNb 1 s 0 @31753 ]
|
| 877 |
"552
|
| 878 |
[v _RB2 `VNb 1 s 0 @31754 ]
|
| 879 |
"553
|
| 880 |
[v _RB3 `VNb 1 s 0 @31755 ]
|
| 881 |
"554
|
| 882 |
[v _RB4 `VNb 1 s 0 @31756 ]
|
| 883 |
"555
|
| 884 |
[v _RB5 `VNb 1 s 0 @31757 ]
|
| 885 |
"556
|
| 886 |
[v _RB6 `VNb 1 s 0 @31758 ]
|
| 887 |
"557
|
| 888 |
[v _RB7 `VNb 1 s 0 @31759 ]
|
| 889 |
"560
|
| 890 |
[v _RA0 `VNb 1 s 0 @31744 ]
|
| 891 |
"561
|
| 892 |
[v _RA1 `VNb 1 s 0 @31745 ]
|
| 893 |
"562
|
| 894 |
[v _RA2 `VNb 1 s 0 @31746 ]
|
| 895 |
"563
|
| 896 |
[v _RA3 `VNb 1 s 0 @31747 ]
|
| 897 |
"564
|
| 898 |
[v _RA4 `VNb 1 s 0 @31748 ]
|
| 899 |
"565
|
| 900 |
[v _RA5 `VNb 1 s 0 @31749 ]
|
| 901 |
"566
|
| 902 |
[v _RA6 `VNb 1 s 0 @31750 ]
|
| 903 |
"12 C:\Programmer\HI-TECH Software\PICC-18\9.50\include\stdio.h
|
| 904 |
[v _ptrdiff_t `i 1 t 2 ]
|
| 905 |
"13
|
| 906 |
[v _size_t `ui 1 t 2 ]
|
| 907 |
"14
|
| 908 |
[v _wchar_t `us 1 t 2 ]
|
| 909 |
"20 C:\Programmer\HI-TECH Software\PICC-18\9.50\include\stdarg.h
|
| 910 |
[v _va_list `*v 1a t 2 ]
|
| 911 |
"61 C:\Programmer\HI-TECH Software\PICC-18\9.50\include\stdio.h
|
| 912 |
[v F838 `(v 1 t 0 ]
|
| 913 |
"62
|
| 914 |
[s S1 __prbuf 4 `*uc 1 ptr 2 0
|
| 915 |
`*F838 1 func 2 2
|
| 916 |
]
|
| 917 |
"12 C:\Documents and Settings\Admin\Skrivebord\SVN\trunk\Embedded\main.c
|
| 918 |
[v _global_Pot_Hi `uc 1 e 1 0 ]
|
| 919 |
[v _global_Pot_Lo `uc 1 e 1 0 ]
|
| 920 |
"13
|
| 921 |
[v F991 `uc 16a t 16 ]
|
| 922 |
[v _global_LCD_Buffer `F991 2a e 32 0 ]
|
| 923 |
"14
|
| 924 |
[v _global_serial_data `uc 1 e 1 0 ]
|
| 925 |
"15
|
| 926 |
[v _global_serial_recieve_buffer `uc 16a e 16 0 ]
|
| 927 |
"16
|
| 928 |
[v _global_recieve_done `b 1 e 0 0 ]
|
| 929 |
"17
|
| 930 |
[v _global_serial_byte_counter `i 1 e 2 0 ]
|
| 931 |
"23
|
| 932 |
[v _ad_init `(v 1 e 0 0 ]
|
| 933 |
{
|
| 934 |
"46
|
| 935 |
} 0
|
| 936 |
"49
|
| 937 |
[v _rs232_init `(v 1 e 0 0 ]
|
| 938 |
{
|
| 939 |
"58
|
| 940 |
} 0
|
| 941 |
"61
|
| 942 |
[v _interrupt_init `(v 1 e 0 0 ]
|
| 943 |
{
|
| 944 |
"68
|
| 945 |
} 0
|
| 946 |
"71
|
| 947 |
[v _pic18_io_init `(v 1 e 0 0 ]
|
| 948 |
{
|
| 949 |
"77
|
| 950 |
} 0
|
| 951 |
"82
|
| 952 |
[v F1008 `(v 1 t 0 ]
|
| 953 |
[v _interrupt_handler `IF1008 1 e 0 0 ]
|
| 954 |
{
|
| 955 |
"89
|
| 956 |
} 0
|
| 957 |
"94
|
| 958 |
[v _serial_send `(v 1 e 0 0 ]
|
| 959 |
{
|
| 960 |
"95
|
| 961 |
[v _i `i 1 a 2 0 ]
|
| 962 |
"96
|
| 963 |
[v _tosend `uc 3a a 3 2 ]
|
| 964 |
"97
|
| 965 |
[v _data `uc 1 a 1 5 ]
|
| 966 |
"106
|
| 967 |
} 6
|
| 968 |
"109
|
| 969 |
[v _serial_recieved `(v 1 e 0 0 ]
|
| 970 |
{
|
| 971 |
"110
|
| 972 |
[v _data `uc 1 a 1 0 ]
|
| 973 |
[v _saved_data `uc 16a a 16 1 ]
|
| 974 |
"125
|
| 975 |
} 17
|
| 976 |
"128
|
| 977 |
[v _main `(v 1 e 0 0 ]
|
| 978 |
{
|
| 979 |
"163
|
| 980 |
} 0
|
| 981 |
[v _lcd_init `(v 0 e 0 0 ]
|
| 982 |
[v _lcd_puts `(v 0 e 0 0 ]
|
| 983 |
[v _lcd_cmd `(v 0 e 0 0 ]
|
| 984 |
[v _DelayMs `(v 0 e 0 0 ]
|
| 985 |
[v _sprintf `(i 0 e 2 0 ]
|
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