1 |
[p AUTOSTATIC LARGE_MODEL SMALL_DATA LFSROK EMI_WORD ]
|
2 |
"19 C:\Programmer\HI-TECH Software\PICC-18\9.50\include\errata.h
|
3 |
[e E1 .
|
4 |
ERRATA_4000 1
|
5 |
ERRATA_FASTINTS 2
|
6 |
ERRATA_LFSR 4
|
7 |
ERRATA_MINUS40 8
|
8 |
ERRATA_RESET 16
|
9 |
ERRATA_BSR15 32
|
10 |
ERRATA_DAW 64
|
11 |
ERRATA_EEDATARD 128
|
12 |
ERRATA_EEADR 256
|
13 |
ERRATA_EE_LVD 512
|
14 |
ERRATA_FL_LVD 1024
|
15 |
ERRATA_TBLWTINT 2048
|
16 |
ERRATA_FW4000 4096
|
17 |
ERRATA_RESETRAM 8192
|
18 |
]
|
19 |
"21 C:\Programmer\HI-TECH Software\PICC-18\9.50\include\pic18fxx2.h
|
20 |
[v _TOSU `VNuc 1 s 1 @4095 ]
|
21 |
"22
|
22 |
[v _TOSH `VNuc 1 s 1 @4094 ]
|
23 |
"23
|
24 |
[v _TOSL `VNuc 1 s 1 @4093 ]
|
25 |
"24
|
26 |
[v _STKPTR `VNuc 1 s 1 @4092 ]
|
27 |
"25
|
28 |
[v _PCLATU `VNuc 1 s 1 @4091 ]
|
29 |
"26
|
30 |
[v _PCLATH `VNuc 1 s 1 @4090 ]
|
31 |
"27
|
32 |
[v _PCL `VNuc 1 s 1 @4089 ]
|
33 |
"28
|
34 |
[v _TBLPTR `*VFuc 1 s 2 @4086 ]
|
35 |
"29
|
36 |
[v _TBLPTRU `VNuc 1 s 1 @4088 ]
|
37 |
"30
|
38 |
[v _TBLPTRH `VNuc 1 s 1 @4087 ]
|
39 |
"31
|
40 |
[v _TBLPTRL `VNuc 1 s 1 @4086 ]
|
41 |
"32
|
42 |
[v _TABLAT `VNuc 1 s 1 @4085 ]
|
43 |
"33
|
44 |
[v _PRODH `VNuc 1 s 1 @4084 ]
|
45 |
"34
|
46 |
[v _PRODL `VNuc 1 s 1 @4083 ]
|
47 |
"35
|
48 |
[v _INTCON `VNuc 1 s 1 @4082 ]
|
49 |
"36
|
50 |
[v _INTCON2 `Nuc 1 s 1 @4081 ]
|
51 |
"37
|
52 |
[v _INTCON3 `VNuc 1 s 1 @4080 ]
|
53 |
"38
|
54 |
[v _INDF0 `VNuc 1 s 1 @4079 ]
|
55 |
"39
|
56 |
[v _POSTINC0 `VNuc 1 s 1 @4078 ]
|
57 |
"40
|
58 |
[v _POSTDEC0 `VNuc 1 s 1 @4077 ]
|
59 |
"41
|
60 |
[v _PREINC0 `VNuc 1 s 1 @4076 ]
|
61 |
"42
|
62 |
[v _PLUSW0 `VNuc 1 s 1 @4075 ]
|
63 |
"43
|
64 |
[v _FSR0H `VNuc 1 s 1 @4074 ]
|
65 |
"44
|
66 |
[v _FSR0L `VNuc 1 s 1 @4073 ]
|
67 |
"45
|
68 |
[v _WREG `VNuc 1 s 1 @4072 ]
|
69 |
"46
|
70 |
[v _INDF1 `VNuc 1 s 1 @4071 ]
|
71 |
"47
|
72 |
[v _POSTINC1 `VNuc 1 s 1 @4070 ]
|
73 |
"48
|
74 |
[v _POSTDEC1 `VNuc 1 s 1 @4069 ]
|
75 |
"49
|
76 |
[v _PREINC1 `VNuc 1 s 1 @4068 ]
|
77 |
"50
|
78 |
[v _PLUSW1 `VNuc 1 s 1 @4067 ]
|
79 |
"51
|
80 |
[v _FSR1H `VNuc 1 s 1 @4066 ]
|
81 |
"52
|
82 |
[v _FSR1L `VNuc 1 s 1 @4065 ]
|
83 |
"53
|
84 |
[v _BSR `Nuc 1 s 1 @4064 ]
|
85 |
"54
|
86 |
[v _INDF2 `VNuc 1 s 1 @4063 ]
|
87 |
"55
|
88 |
[v _POSTINC2 `VNuc 1 s 1 @4062 ]
|
89 |
"56
|
90 |
[v _POSTDEC2 `VNuc 1 s 1 @4061 ]
|
91 |
"57
|
92 |
[v _PREINC2 `VNuc 1 s 1 @4060 ]
|
93 |
"58
|
94 |
[v _PLUSW2 `VNuc 1 s 1 @4059 ]
|
95 |
"59
|
96 |
[v _FSR2H `VNuc 1 s 1 @4058 ]
|
97 |
"60
|
98 |
[v _FSR2L `VNuc 1 s 1 @4057 ]
|
99 |
"61
|
100 |
[v _STATUS `VNuc 1 s 1 @4056 ]
|
101 |
"62
|
102 |
[v _TMR0 `VNui 1 s 2 @4054 ]
|
103 |
"63
|
104 |
[v _TMR0H `VNuc 1 s 1 @4055 ]
|
105 |
"64
|
106 |
[v _TMR0L `VNuc 1 s 1 @4054 ]
|
107 |
"65
|
108 |
[v _T0CON `Nuc 1 s 1 @4053 ]
|
109 |
"66
|
110 |
[v _OSCCON `VNuc 1 s 1 @4051 ]
|
111 |
"67
|
112 |
[v _LVDCON `VNuc 1 s 1 @4050 ]
|
113 |
"68
|
114 |
[v _WDTCON `Nuc 1 s 1 @4049 ]
|
115 |
"69
|
116 |
[v _RCON `VNuc 1 s 1 @4048 ]
|
117 |
"70
|
118 |
[v _TMR1 `VNui 1 s 2 @4046 ]
|
119 |
"71
|
120 |
[v _TMR1H `VNuc 1 s 1 @4047 ]
|
121 |
"72
|
122 |
[v _TMR1L `VNuc 1 s 1 @4046 ]
|
123 |
"73
|
124 |
[v _T1CON `Nuc 1 s 1 @4045 ]
|
125 |
"74
|
126 |
[v _TMR2 `VNuc 1 s 1 @4044 ]
|
127 |
"75
|
128 |
[v _PR2 `VNuc 1 s 1 @4043 ]
|
129 |
"76
|
130 |
[v _T2CON `Nuc 1 s 1 @4042 ]
|
131 |
"77
|
132 |
[v _SSPBUF `VNuc 1 s 1 @4041 ]
|
133 |
"78
|
134 |
[v _SSPADD `VNuc 1 s 1 @4040 ]
|
135 |
"79
|
136 |
[v _SSPSTAT `VNuc 1 s 1 @4039 ]
|
137 |
"80
|
138 |
[v _SSPCON1 `VNuc 1 s 1 @4038 ]
|
139 |
"81
|
140 |
[v _SSPCON2 `VNuc 1 s 1 @4037 ]
|
141 |
"82
|
142 |
[v _ADRES `VNui 1 s 2 @4035 ]
|
143 |
"83
|
144 |
[v _ADRESH `VNuc 1 s 1 @4036 ]
|
145 |
"84
|
146 |
[v _ADRESL `VNuc 1 s 1 @4035 ]
|
147 |
"85
|
148 |
[v _ADCON0 `VNuc 1 s 1 @4034 ]
|
149 |
"86
|
150 |
[v _ADCON1 `Nuc 1 s 1 @4033 ]
|
151 |
"87
|
152 |
[v _CCPR1 `VNui 1 s 2 @4030 ]
|
153 |
"88
|
154 |
[v _CCPR1H `VNuc 1 s 1 @4031 ]
|
155 |
"89
|
156 |
[v _CCPR1L `VNuc 1 s 1 @4030 ]
|
157 |
"90
|
158 |
[v _CCP1CON `VNuc 1 s 1 @4029 ]
|
159 |
"91
|
160 |
[v _CCPR2 `VNui 1 s 2 @4027 ]
|
161 |
"92
|
162 |
[v _CCPR2H `VNuc 1 s 1 @4028 ]
|
163 |
"93
|
164 |
[v _CCPR2L `VNuc 1 s 1 @4027 ]
|
165 |
"94
|
166 |
[v _CCP2CON `VNuc 1 s 1 @4026 ]
|
167 |
"95
|
168 |
[v _TMR3 `VNui 1 s 2 @4018 ]
|
169 |
"96
|
170 |
[v _TMR3H `VNuc 1 s 1 @4019 ]
|
171 |
"97
|
172 |
[v _TMR3L `VNuc 1 s 1 @4018 ]
|
173 |
"98
|
174 |
[v _T3CON `Nuc 1 s 1 @4017 ]
|
175 |
"99
|
176 |
[v _SPBRG `Nuc 1 s 1 @4015 ]
|
177 |
"100
|
178 |
[v _RCREG `VNuc 1 s 1 @4014 ]
|
179 |
"101
|
180 |
[v _TXREG `VNuc 1 s 1 @4013 ]
|
181 |
"102
|
182 |
[v _TXSTA `VNuc 1 s 1 @4012 ]
|
183 |
"103
|
184 |
[v _RCSTA `VNuc 1 s 1 @4011 ]
|
185 |
"104
|
186 |
[v _EEADR `VNuc 1 s 1 @4009 ]
|
187 |
"105
|
188 |
[v _EEDATA `VNuc 1 s 1 @4008 ]
|
189 |
"106
|
190 |
[v _EECON2 `VNuc 1 s 1 @4007 ]
|
191 |
"107
|
192 |
[v _EECON1 `VNuc 1 s 1 @4006 ]
|
193 |
"108
|
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[v _IPR2 `Nuc 1 s 1 @4002 ]
|
195 |
"109
|
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[v _PIR2 `VNuc 1 s 1 @4001 ]
|
197 |
"110
|
198 |
[v _PIE2 `Nuc 1 s 1 @4000 ]
|
199 |
"111
|
200 |
[v _IPR1 `Nuc 1 s 1 @3999 ]
|
201 |
"112
|
202 |
[v _PIR1 `VNuc 1 s 1 @3998 ]
|
203 |
"113
|
204 |
[v _PIE1 `Nuc 1 s 1 @3997 ]
|
205 |
"114
|
206 |
[v _TRISC `VNuc 1 s 1 @3988 ]
|
207 |
"115
|
208 |
[v _TRISB `VNuc 1 s 1 @3987 ]
|
209 |
"116
|
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[v _TRISA `VNuc 1 s 1 @3986 ]
|
211 |
"117
|
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[v _LATC `VNuc 1 s 1 @3979 ]
|
213 |
"118
|
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[v _LATB `VNuc 1 s 1 @3978 ]
|
215 |
"119
|
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[v _LATA `VNuc 1 s 1 @3977 ]
|
217 |
"120
|
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[v _PORTC `VNuc 1 s 1 @3970 ]
|
219 |
"121
|
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[v _PORTB `VNuc 1 s 1 @3969 ]
|
221 |
"122
|
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[v _PORTA `VNuc 1 s 1 @3968 ]
|
223 |
"124
|
224 |
[v _TRISE `VNuc 1 s 1 @3990 ]
|
225 |
"125
|
226 |
[v _TRISD `VNuc 1 s 1 @3989 ]
|
227 |
"126
|
228 |
[v _LATE `VNuc 1 s 1 @3981 ]
|
229 |
"127
|
230 |
[v _LATD `VNuc 1 s 1 @3980 ]
|
231 |
"128
|
232 |
[v _PORTE `VNuc 1 s 1 @3972 ]
|
233 |
"129
|
234 |
[v _PORTD `VNuc 1 s 1 @3971 ]
|
235 |
"134
|
236 |
[v _NEGATIVE `VNb 1 s 0 @32452 ]
|
237 |
"135
|
238 |
[v _OVERFLOW `VNb 1 s 0 @32451 ]
|
239 |
"136
|
240 |
[v _ZERO `VNb 1 s 0 @32450 ]
|
241 |
"137
|
242 |
[v _DC `VNb 1 s 0 @32449 ]
|
243 |
"138
|
244 |
[v _CARRY `VNb 1 s 0 @32448 ]
|
245 |
"141
|
246 |
[v _STKFUL `VNb 1 s 0 @32743 ]
|
247 |
"142
|
248 |
[v _STKUNF `VNb 1 s 0 @32742 ]
|
249 |
"143
|
250 |
[v _SP4 `VNb 1 s 0 @32740 ]
|
251 |
"144
|
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[v _SP3 `VNb 1 s 0 @32739 ]
|
253 |
"145
|
254 |
[v _SP2 `VNb 1 s 0 @32738 ]
|
255 |
"146
|
256 |
[v _SP1 `VNb 1 s 0 @32737 ]
|
257 |
"147
|
258 |
[v _SP0 `VNb 1 s 0 @32736 ]
|
259 |
"150
|
260 |
[v _GIE `Nb 1 s 0 @32663 ]
|
261 |
"151
|
262 |
[v _GIEH `Nb 1 s 0 @32663 ]
|
263 |
"152
|
264 |
[v _PEIE `Nb 1 s 0 @32662 ]
|
265 |
"153
|
266 |
[v _GIEL `Nb 1 s 0 @32662 ]
|
267 |
"154
|
268 |
[v _TMR0IE `Nb 1 s 0 @32661 ]
|
269 |
"155
|
270 |
[v _INT0IE `Nb 1 s 0 @32660 ]
|
271 |
"156
|
272 |
[v _RBIE `Nb 1 s 0 @32659 ]
|
273 |
"157
|
274 |
[v _TMR0IF `VNb 1 s 0 @32658 ]
|
275 |
"158
|
276 |
[v _INT0IF `VNb 1 s 0 @32657 ]
|
277 |
"159
|
278 |
[v _RBIF `VNb 1 s 0 @32656 ]
|
279 |
"160
|
280 |
[v _T0IF `VNb 1 s 0 @32658 ]
|
281 |
"163
|
282 |
[v _RBPU `Nb 1 s 0 @32655 ]
|
283 |
"164
|
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[v _INTEDG0 `Nb 1 s 0 @32654 ]
|
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"165
|
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[v _INTEDG1 `Nb 1 s 0 @32653 ]
|
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"166
|
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[v _INTEDG2 `Nb 1 s 0 @32652 ]
|
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"167
|
290 |
[v _TMR0IP `Nb 1 s 0 @32650 ]
|
291 |
"168
|
292 |
[v _RBIP `Nb 1 s 0 @32648 ]
|
293 |
"169
|
294 |
[v _T0IP `Nb 1 s 0 @32650 ]
|
295 |
"172
|
296 |
[v _INT2IP `Nb 1 s 0 @32647 ]
|
297 |
"173
|
298 |
[v _INT1IP `Nb 1 s 0 @32646 ]
|
299 |
"174
|
300 |
[v _INT2IE `Nb 1 s 0 @32644 ]
|
301 |
"175
|
302 |
[v _INT1IE `Nb 1 s 0 @32643 ]
|
303 |
"176
|
304 |
[v _INT2IF `VNb 1 s 0 @32641 ]
|
305 |
"177
|
306 |
[v _INT1IF `VNb 1 s 0 @32640 ]
|
307 |
"180
|
308 |
[v _TMR0ON `Nb 1 s 0 @32431 ]
|
309 |
"181
|
310 |
[v _T08BIT `Nb 1 s 0 @32430 ]
|
311 |
"182
|
312 |
[v _T0CS `Nb 1 s 0 @32429 ]
|
313 |
"183
|
314 |
[v _T0SE `Nb 1 s 0 @32428 ]
|
315 |
"184
|
316 |
[v _PSA `Nb 1 s 0 @32427 ]
|
317 |
"185
|
318 |
[v _T0PS2 `Nb 1 s 0 @32426 ]
|
319 |
"186
|
320 |
[v _T0PS1 `Nb 1 s 0 @32425 ]
|
321 |
"187
|
322 |
[v _T0PS0 `Nb 1 s 0 @32424 ]
|
323 |
"190
|
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[v _SCS `Nb 1 s 0 @32408 ]
|
325 |
"193
|
326 |
[v _IRVST `VNb 1 s 0 @32405 ]
|
327 |
"194
|
328 |
[v _LVDEN `Nb 1 s 0 @32404 ]
|
329 |
"195
|
330 |
[v _LVDL3 `Nb 1 s 0 @32403 ]
|
331 |
"196
|
332 |
[v _LVDL2 `Nb 1 s 0 @32402 ]
|
333 |
"197
|
334 |
[v _LVDL1 `Nb 1 s 0 @32401 ]
|
335 |
"198
|
336 |
[v _LVDL0 `Nb 1 s 0 @32400 ]
|
337 |
"201
|
338 |
[v _SWDTEN `Nb 1 s 0 @32392 ]
|
339 |
"204
|
340 |
[v _IPEN `Nb 1 s 0 @32391 ]
|
341 |
"205
|
342 |
[v _RI `VNb 1 s 0 @32388 ]
|
343 |
"206
|
344 |
[v _TO `VNb 1 s 0 @32387 ]
|
345 |
"207
|
346 |
[v _PD `VNb 1 s 0 @32386 ]
|
347 |
"208
|
348 |
[v _POR `VNb 1 s 0 @32385 ]
|
349 |
"209
|
350 |
[v _BOR `VNb 1 s 0 @32384 ]
|
351 |
"212
|
352 |
[v _RD16 `Nb 1 s 0 @32367 ]
|
353 |
"213
|
354 |
[v _T1RD16 `Nb 1 s 0 @32367 ]
|
355 |
"214
|
356 |
[v _T1CKPS1 `Nb 1 s 0 @32365 ]
|
357 |
"215
|
358 |
[v _T1CKPS0 `Nb 1 s 0 @32364 ]
|
359 |
"216
|
360 |
[v _T1OSCEN `Nb 1 s 0 @32363 ]
|
361 |
"217
|
362 |
[v _T1SYNC `Nb 1 s 0 @32362 ]
|
363 |
"218
|
364 |
[v _TMR1CS `Nb 1 s 0 @32361 ]
|
365 |
"219
|
366 |
[v _TMR1ON `Nb 1 s 0 @32360 ]
|
367 |
"222
|
368 |
[v _TOUTPS3 `Nb 1 s 0 @32342 ]
|
369 |
"223
|
370 |
[v _TOUTPS2 `Nb 1 s 0 @32341 ]
|
371 |
"224
|
372 |
[v _TOUTPS1 `Nb 1 s 0 @32340 ]
|
373 |
"225
|
374 |
[v _TOUTPS0 `Nb 1 s 0 @32339 ]
|
375 |
"226
|
376 |
[v _TMR2ON `Nb 1 s 0 @32338 ]
|
377 |
"227
|
378 |
[v _T2CKPS1 `Nb 1 s 0 @32337 ]
|
379 |
"228
|
380 |
[v _T2CKPS0 `Nb 1 s 0 @32336 ]
|
381 |
"231
|
382 |
[v _SMP `Nb 1 s 0 @32319 ]
|
383 |
"232
|
384 |
[v _CKE `Nb 1 s 0 @32318 ]
|
385 |
"233
|
386 |
[v _DA `VNb 1 s 0 @32317 ]
|
387 |
"234
|
388 |
[v _P `VNb 1 s 0 @32316 ]
|
389 |
"235
|
390 |
[v _S `VNb 1 s 0 @32315 ]
|
391 |
"236
|
392 |
[v _RW `VNb 1 s 0 @32314 ]
|
393 |
"237
|
394 |
[v _UA `VNb 1 s 0 @32313 ]
|
395 |
"238
|
396 |
[v _BF `VNb 1 s 0 @32312 ]
|
397 |
"240
|
398 |
[v _STOP `VNb 1 s 0 @32316 ]
|
399 |
"241
|
400 |
[v _START `VNb 1 s 0 @32315 ]
|
401 |
"244
|
402 |
[v _WCOL `VNb 1 s 0 @32311 ]
|
403 |
"245
|
404 |
[v _SSPOV `VNb 1 s 0 @32310 ]
|
405 |
"246
|
406 |
[v _SSPEN `Nb 1 s 0 @32309 ]
|
407 |
"247
|
408 |
[v _CKP `Nb 1 s 0 @32308 ]
|
409 |
"248
|
410 |
[v _SSPM3 `Nb 1 s 0 @32307 ]
|
411 |
"249
|
412 |
[v _SSPM2 `Nb 1 s 0 @32306 ]
|
413 |
"250
|
414 |
[v _SSPM1 `Nb 1 s 0 @32305 ]
|
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"251
|
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[v _SSPM0 `Nb 1 s 0 @32304 ]
|
417 |
"254
|
418 |
[v _GCEN `Nb 1 s 0 @32303 ]
|
419 |
"255
|
420 |
[v _ACKSTAT `VNb 1 s 0 @32302 ]
|
421 |
"256
|
422 |
[v _ACKDT `VNb 1 s 0 @32301 ]
|
423 |
"257
|
424 |
[v _ACKEN `VNb 1 s 0 @32300 ]
|
425 |
"258
|
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[v _RCEN `Nb 1 s 0 @32299 ]
|
427 |
"259
|
428 |
[v _PEN `VNb 1 s 0 @32298 ]
|
429 |
"260
|
430 |
[v _RSEN `VNb 1 s 0 @32297 ]
|
431 |
"261
|
432 |
[v _SEN `VNb 1 s 0 @32296 ]
|
433 |
"264
|
434 |
[v _ADCS1 `Nb 1 s 0 @32279 ]
|
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"265
|
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[v _ADCS0 `Nb 1 s 0 @32278 ]
|
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"266
|
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[v _CHS2 `Nb 1 s 0 @32277 ]
|
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"267
|
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[v _CHS1 `Nb 1 s 0 @32276 ]
|
441 |
"268
|
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[v _CHS0 `Nb 1 s 0 @32275 ]
|
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"269
|
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[v _GODONE `VNb 1 s 0 @32274 ]
|
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"270
|
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[v _ADON `Nb 1 s 0 @32272 ]
|
447 |
"273
|
448 |
[v _ADFM `Nb 1 s 0 @32271 ]
|
449 |
"274
|
450 |
[v _ADCS2 `Nb 1 s 0 @32270 ]
|
451 |
"275
|
452 |
[v _PCFG3 `Nb 1 s 0 @32267 ]
|
453 |
"276
|
454 |
[v _PCFG2 `Nb 1 s 0 @32266 ]
|
455 |
"277
|
456 |
[v _PCFG1 `Nb 1 s 0 @32265 ]
|
457 |
"278
|
458 |
[v _PCFG0 `Nb 1 s 0 @32264 ]
|
459 |
"281
|
460 |
[v _DC1B1 `VNb 1 s 0 @32237 ]
|
461 |
"282
|
462 |
[v _DC1B0 `VNb 1 s 0 @32236 ]
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463 |
"283
|
464 |
[v _CCP1M3 `Nb 1 s 0 @32235 ]
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465 |
"284
|
466 |
[v _CCP1M2 `Nb 1 s 0 @32234 ]
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467 |
"285
|
468 |
[v _CCP1M1 `Nb 1 s 0 @32233 ]
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469 |
"286
|
470 |
[v _CCP1M0 `Nb 1 s 0 @32232 ]
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471 |
"289
|
472 |
[v _DC2B1 `VNb 1 s 0 @32213 ]
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473 |
"290
|
474 |
[v _DC2B0 `VNb 1 s 0 @32212 ]
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475 |
"291
|
476 |
[v _CCP2M3 `Nb 1 s 0 @32211 ]
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477 |
"292
|
478 |
[v _CCP2M2 `Nb 1 s 0 @32210 ]
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479 |
"293
|
480 |
[v _CCP2M1 `Nb 1 s 0 @32209 ]
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481 |
"294
|
482 |
[v _CCP2M0 `Nb 1 s 0 @32208 ]
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483 |
"297
|
484 |
[v _T3RD16 `Nb 1 s 0 @32143 ]
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485 |
"298
|
486 |
[v _T3CCP2 `Nb 1 s 0 @32142 ]
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487 |
"299
|
488 |
[v _T3CKPS1 `Nb 1 s 0 @32141 ]
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489 |
"300
|
490 |
[v _T3CKPS0 `Nb 1 s 0 @32140 ]
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491 |
"301
|
492 |
[v _T3CCP1 `Nb 1 s 0 @32139 ]
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493 |
"302
|
494 |
[v _T3SYNC `Nb 1 s 0 @32138 ]
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495 |
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|
496 |
[v _TMR3CS `Nb 1 s 0 @32137 ]
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497 |
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|
498 |
[v _TMR3ON `Nb 1 s 0 @32136 ]
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499 |
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|
500 |
[v _CSRC `Nb 1 s 0 @32103 ]
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501 |
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|
502 |
[v _TX9 `Nb 1 s 0 @32102 ]
|
503 |
"309
|
504 |
[v _TXEN `Nb 1 s 0 @32101 ]
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505 |
"310
|
506 |
[v _SYNC `Nb 1 s 0 @32100 ]
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507 |
"311
|
508 |
[v _BRGH `Nb 1 s 0 @32098 ]
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509 |
"312
|
510 |
[v _TRMT `VNb 1 s 0 @32097 ]
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511 |
"313
|
512 |
[v _TX9D `Nb 1 s 0 @32096 ]
|
513 |
"316
|
514 |
[v _SPEN `Nb 1 s 0 @32095 ]
|
515 |
"317
|
516 |
[v _RX9 `Nb 1 s 0 @32094 ]
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517 |
"318
|
518 |
[v _SREN `Nb 1 s 0 @32093 ]
|
519 |
"319
|
520 |
[v _CREN `Nb 1 s 0 @32092 ]
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521 |
"320
|
522 |
[v _ADDEN `Nb 1 s 0 @32091 ]
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523 |
"321
|
524 |
[v _FERR `VNb 1 s 0 @32090 ]
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525 |
"322
|
526 |
[v _OERR `VNb 1 s 0 @32089 ]
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527 |
"323
|
528 |
[v _RX9D `VNb 1 s 0 @32088 ]
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529 |
"326
|
530 |
[v _EEPGD `Nb 1 s 0 @32055 ]
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531 |
"327
|
532 |
[v _CFGS `Nb 1 s 0 @32054 ]
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533 |
"329
|
534 |
[v _EEFS `Nb 1 s 0 @32054 ]
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535 |
"330
|
536 |
[v _FREE `VNb 1 s 0 @32052 ]
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537 |
"331
|
538 |
[v _WRERR `VNb 1 s 0 @32051 ]
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539 |
"332
|
540 |
[v _WREN `VNb 1 s 0 @32050 ]
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541 |
"333
|
542 |
[v _WR `VNb 1 s 0 @32049 ]
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543 |
"334
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544 |
[v _RD `VNb 1 s 0 @32048 ]
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545 |
"337
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546 |
[v _EEIP `Nb 1 s 0 @32020 ]
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547 |
"338
|
548 |
[v _BCLIP `Nb 1 s 0 @32019 ]
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549 |
"339
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550 |
[v _LVDIP `Nb 1 s 0 @32018 ]
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551 |
"340
|
552 |
[v _TMR3IP `Nb 1 s 0 @32017 ]
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553 |
"341
|
554 |
[v _CCP2IP `Nb 1 s 0 @32016 ]
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555 |
"344
|
556 |
[v _EEIF `VNb 1 s 0 @32012 ]
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557 |
"345
|
558 |
[v _BCLIF `VNb 1 s 0 @32011 ]
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559 |
"346
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560 |
[v _LVDIF `VNb 1 s 0 @32010 ]
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561 |
"347
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562 |
[v _TMR3IF `VNb 1 s 0 @32009 ]
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563 |
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|
564 |
[v _CCP2IF `VNb 1 s 0 @32008 ]
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565 |
"351
|
566 |
[v _EEIE `Nb 1 s 0 @32004 ]
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567 |
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568 |
[v _BCLIE `Nb 1 s 0 @32003 ]
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569 |
"353
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570 |
[v _LVDIE `Nb 1 s 0 @32002 ]
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571 |
"354
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572 |
[v _TMR3IE `Nb 1 s 0 @32001 ]
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573 |
"355
|
574 |
[v _CCP2IE `Nb 1 s 0 @32000 ]
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575 |
"358
|
576 |
[v _PSPIP `Nb 1 s 0 @31999 ]
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577 |
"359
|
578 |
[v _ADIP `Nb 1 s 0 @31998 ]
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579 |
"360
|
580 |
[v _RCIP `Nb 1 s 0 @31997 ]
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581 |
"361
|
582 |
[v _TXIP `Nb 1 s 0 @31996 ]
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583 |
"362
|
584 |
[v _SSPIP `Nb 1 s 0 @31995 ]
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585 |
"363
|
586 |
[v _CCP1IP `Nb 1 s 0 @31994 ]
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587 |
"364
|
588 |
[v _TMR2IP `Nb 1 s 0 @31993 ]
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589 |
"365
|
590 |
[v _TMR1IP `Nb 1 s 0 @31992 ]
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591 |
"368
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592 |
[v _PSPIF `VNb 1 s 0 @31991 ]
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593 |
"369
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594 |
[v _ADIF `VNb 1 s 0 @31990 ]
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595 |
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596 |
[v _RCIF `VNb 1 s 0 @31989 ]
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597 |
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598 |
[v _TXIF `VNb 1 s 0 @31988 ]
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599 |
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600 |
[v _SSPIF `VNb 1 s 0 @31987 ]
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601 |
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602 |
[v _CCP1IF `VNb 1 s 0 @31986 ]
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603 |
"374
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604 |
[v _TMR2IF `VNb 1 s 0 @31985 ]
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605 |
"375
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606 |
[v _TMR1IF `VNb 1 s 0 @31984 ]
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607 |
"378
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608 |
[v _PSPIE `Nb 1 s 0 @31983 ]
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609 |
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610 |
[v _ADIE `Nb 1 s 0 @31982 ]
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611 |
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|
612 |
[v _RCIE `Nb 1 s 0 @31981 ]
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613 |
"381
|
614 |
[v _TXIE `Nb 1 s 0 @31980 ]
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615 |
"382
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616 |
[v _SSPIE `Nb 1 s 0 @31979 ]
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617 |
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618 |
[v _CCP1IE `Nb 1 s 0 @31978 ]
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619 |
"384
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620 |
[v _TMR2IE `Nb 1 s 0 @31977 ]
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621 |
"385
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622 |
[v _TMR1IE `Nb 1 s 0 @31976 ]
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623 |
"389
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624 |
[v _IBF `VNb 1 s 0 @31927 ]
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625 |
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626 |
[v _OBF `VNb 1 s 0 @31926 ]
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627 |
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628 |
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629 |
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630 |
[v _PSPMODE `VNb 1 s 0 @31924 ]
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631 |
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632 |
[v _TRISE2 `VNb 1 s 0 @31922 ]
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634 |
[v _TRISE1 `VNb 1 s 0 @31921 ]
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635 |
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636 |
[v _TRISE0 `VNb 1 s 0 @31920 ]
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638 |
[v _TRISD7 `VNb 1 s 0 @31919 ]
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639 |
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[v _TRISD6 `VNb 1 s 0 @31918 ]
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[v _TRISC7 `VNb 1 s 0 @31911 ]
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[v _TRISC2 `VNb 1 s 0 @31906 ]
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733 |
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[v _LATD4 `VNb 1 s 0 @31844 ]
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[v _LATD7 `VNb 1 s 0 @31847 ]
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[v _LC0 `VNb 1 s 0 @31832 ]
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[v _LATA1 `VNb 1 s 0 @31817 ]
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[v _LATA3 `VNb 1 s 0 @31819 ]
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[v _LATA4 `VNb 1 s 0 @31820 ]
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[v _LATA5 `VNb 1 s 0 @31821 ]
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[v _LATA6 `VNb 1 s 0 @31822 ]
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[v _RD2 `VNb 1 s 0 @31770 ]
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889 |
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|
890 |
[v _RA0 `VNb 1 s 0 @31744 ]
|
891 |
"561
|
892 |
[v _RA1 `VNb 1 s 0 @31745 ]
|
893 |
"562
|
894 |
[v _RA2 `VNb 1 s 0 @31746 ]
|
895 |
"563
|
896 |
[v _RA3 `VNb 1 s 0 @31747 ]
|
897 |
"564
|
898 |
[v _RA4 `VNb 1 s 0 @31748 ]
|
899 |
"565
|
900 |
[v _RA5 `VNb 1 s 0 @31749 ]
|
901 |
"566
|
902 |
[v _RA6 `VNb 1 s 0 @31750 ]
|
903 |
"14 c:\Documents and Settings\Admin\Skrivebord\SVN\trunk\Embedded\lcd.c
|
904 |
[v _fourbit `b 1 s 0 0 ]
|
905 |
"67
|
906 |
[v _lcd_cmd `(v 1 e 0 0 ]
|
907 |
{
|
908 |
[v _c `uc 1 a 1 wreg ]
|
909 |
"68
|
910 |
[v _c `uc 1 a 1 0 ]
|
911 |
"82
|
912 |
} 1
|
913 |
"87
|
914 |
[v _lcd_data `(v 1 e 0 0 ]
|
915 |
{
|
916 |
[v _c `uc 1 a 1 wreg ]
|
917 |
"88
|
918 |
[v _c `uc 1 a 1 0 ]
|
919 |
"106
|
920 |
} 1
|
921 |
"112
|
922 |
[v _lcd_puts `(v 1 e 0 0 ]
|
923 |
{
|
924 |
[v _s `*Cuc 1 p 2 0 ]
|
925 |
"115
|
926 |
} 0
|
927 |
"120
|
928 |
[v _lcd_init `(v 1 e 0 0 ]
|
929 |
{
|
930 |
[v _mode `uc 1 a 1 wreg ]
|
931 |
"121
|
932 |
[v _init_value `uc 1 a 1 0 ]
|
933 |
"124
|
934 |
[v _mode `uc 1 a 1 1 ]
|
935 |
"143
|
936 |
{
|
937 |
[v __dcnt `uc 1 a 1 2 ]
|
938 |
}
|
939 |
"160
|
940 |
} 3
|
941 |
[v _DelayMs `(v 0 e 0 0 ]
|