Include/TCPIP%20Stack/ETH97J60.h

/*********************************************************************
 *
 *            Ethernet registers/bits for PIC18F97J60
 *
 *********************************************************************
 * FileName:        ETH97J60.h
 * Description:         Include file for Ethernet related data structures 
 *                                      constants.
 * Company:         Microchip Technology, Inc.
 *
 * Software License Agreement
 *
 * Copyright © 2002-2007 Microchip Technology Inc.  All rights 
 * reserved.
 *
 * Microchip licenses to you the right to use, modify, copy, and 
 * distribute: 
 * (i)  the Software when embedded on a Microchip microcontroller or 
 *      digital signal controller product (“Device”) which is 
 *      integrated into Licensee’s product; or
 * (ii) ONLY the Software driver source files ENC28J60.c and 
 *      ENC28J60.h ported to a non-Microchip device used in 
 *      conjunction with a Microchip ethernet controller for the 
 *      sole purpose of interfacing with the ethernet controller. 
 *
 * You should refer to the license agreement accompanying this 
 * Software for additional information regarding your rights and 
 * obligations.
 *
 * THE SOFTWARE AND DOCUMENTATION ARE PROVIDED “AS IS” WITHOUT 
 * WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT 
 * LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
 * PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL 
 * MICROCHIP BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR 
 * CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF 
 * PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS 
 * BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE 
 * THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER 
 * SIMILAR COSTS, WHETHER ASSERTED ON THE BASIS OF CONTRACT, TORT 
 * (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR OTHERWISE.
 *
 *
 * Author               Date        Comment
 *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 * Howard Schlunder             06/12/05        Modified for 97J60 (from ENC28J60)
 * Howard Schlunder             03/23/06        Updated for Advance Data Sheet
 * Howard Schlunder             06/29/06        Changed MACON3_PHDRLEN to MACON3_PHDREN
 * Howard Schlunder             09/13/06        Removed a lot of bits for 
 *                                                                      preliminary data sheet, added RXAPDIS
 ********************************************************************/

#ifndef __ETH97J60_H
#define __ETH97J60_H
#include "GenericTypeDefs.h"

typedef union {
        BYTE v[7];
        struct {
                WORD     ByteCount;
                unsigned CollisionCount:4;
                unsigned CRCError:1;
                unsigned LengthCheckError:1;
                unsigned LengthOutOfRange:1;
                unsigned Done:1;
                unsigned Multicast:1;
                unsigned Broadcast:1;
                unsigned PacketDefer:1;
                unsigned ExcessiveDefer:1;
                unsigned MaximumCollisions:1;
                unsigned LateCollision:1;
                unsigned Giant:1;
                unsigned Underrun:1;
                WORD     BytesTransmittedOnWire;
                unsigned ControlFrame:1;
                unsigned PAUSEControlFrame:1;
                unsigned BackpressureApplied:1;
                unsigned VLANTaggedFrame:1;
                unsigned Zeros:4;
        } bits;
} TXSTATUS;

typedef union {
        BYTE v[4];
        struct {
                WORD     ByteCount;
                unsigned PreviouslyIgnored:1;
                unsigned RXDCPreviouslySeen:1;
                unsigned CarrierPreviouslySeen:1;
                unsigned CodeViolation:1;
                unsigned CRCError:1;
                unsigned LengthCheckError:1;
                unsigned LengthOutOfRange:1;
                unsigned ReceiveOk:1;
                unsigned Multicast:1;
                unsigned Broadcast:1;
                unsigned DribbleNibble:1;
                unsigned ControlFrame:1;
                unsigned PauseControlFrame:1;
                unsigned UnsupportedOpcode:1;
                unsigned VLANType:1;
                unsigned Zero:1;
        } bits;
} RXSTATUS;


/******************************************************************************
* PHY Register Locations
******************************************************************************/
#define PHCON1  0x00
#define PHSTAT1 0x01
#define PHCON2  0x10
#define PHSTAT2 0x11
#define PHIE    0x12
#define PHIR    0x13
#define PHLCON  0x14


typedef union {
        WORD Val;
        WORD_VAL VAL;

        // PHCON1 bits ----------
        struct {
                unsigned :8;
                unsigned PDPXMD:1;
                unsigned :7;
        } PHCON1bits;

        // PHSTAT1 bits --------
        struct {
                unsigned :2;
                unsigned LLSTAT:1;
                unsigned :5;
                unsigned :8;
        } PHSTAT1bits;

        // PHCON2 bits ----------
        struct {
                unsigned :4;
                unsigned RXAPDIS:1;
                unsigned :3;
                unsigned HDLDIS:1;
                unsigned :5;
                unsigned FRCLNK:1;
                unsigned :1;
        } PHCON2bits;

        // PHSTAT2 bits --------
        struct {
                unsigned :8;
                unsigned :2;
                unsigned LSTAT:1;
                unsigned COLSTAT:1;
                unsigned RXSTAT:1;
                unsigned TXSTAT:1;
                unsigned :2;
        } PHSTAT2bits;

        // PHIE bits -----------
        struct {
                unsigned :1;
                unsigned PGEIE:1;
                unsigned :2;
                unsigned PLNKIE:1;
                unsigned :3;
                unsigned :8;
        } PHIEbits;

        // PHIR bits -----------
        struct {
                unsigned :2;
                unsigned PGIF:1;
                unsigned :1;
                unsigned PLNKIF:1;
                unsigned :3;
                unsigned :8;
        } PHIRbits;

        // PHLCON bits -------
        struct {
                unsigned :1;
                unsigned STRCH:1;
                unsigned LFRQ0:1;
                unsigned LFRQ1:1;
                unsigned LBCFG0:1;
                unsigned LBCFG1:1;
                unsigned LBCFG2:1;
                unsigned LBCFG3:1;
                unsigned LACFG0:1;
                unsigned LACFG1:1;
                unsigned LACFG2:1;
                unsigned LACFG3:1;
                unsigned :4;
        } PHLCONbits;
        struct {
                unsigned :1;
                unsigned STRCH:1;
                unsigned LFRQ:2;
                unsigned LBCFG:4;
                unsigned LACFG:4;
                unsigned :4;
        } PHLCONbits2;
} PHYREG;


/******************************************************************************
* Individual Register Bits
******************************************************************************/
// ETH/MAC/MII bits

// EIE bits ----------
#define EIE_PKTIE               (1<<6)
#define EIE_DMAIE               (1<<5)
#define EIE_LINKIE              (1<<4)
#define EIE_TXIE                (1<<3)
#define EIE_TXERIE              (1<<1)
#define EIE_RXERIE              (1)

// EIR bits ----------
#define EIR_PKTIF               (1<<6)
#define EIR_DMAIF               (1<<5)
#define EIR_LINKIF              (1<<4)
#define EIR_TXIF                (1<<3)
#define EIR_TXERIF              (1<<1)
#define EIR_RXERIF              (1)
        
// ESTAT bits ---------
#define ESTAT_BUFER             (1<<6)
#define ESTAT_RXBUSY    (1<<2)
#define ESTAT_TXABRT    (1<<1)
#define ESTAT_PHYRDY    (1)
        
// ECON2 bits --------
#define ECON2_AUTOINC   (1<<7)
#define ECON2_PKTDEC    (1<<6)
#define ECON2_ETHEN             (1<<5)
        
// ECON1 bits --------
#define ECON1_TXRST             (1<<7)
#define ECON1_RXRST             (1<<6)
#define ECON1_DMAST             (1<<5)
#define ECON1_CSUMEN    (1<<4)
#define ECON1_TXRTS             (1<<3)
#define ECON1_RXEN              (1<<2)
        
// ERXFCON bits ------
#define ERXFCON_UCEN    (1<<7)
#define ERXFCON_ANDOR   (1<<6)
#define ERXFCON_CRCEN   (1<<5)
#define ERXFCON_PMEN    (1<<4)
#define ERXFCON_MPEN    (1<<3)
#define ERXFCON_HTEN    (1<<2)
#define ERXFCON_MCEN    (1<<1)
#define ERXFCON_BCEN    (1)
        
// MACON1 bits --------
#define MACON1_TXPAUS   (1<<3)
#define MACON1_RXPAUS   (1<<2)
#define MACON1_PASSALL  (1<<1)
#define MACON1_MARXEN   (1)
        
// MACON3 bits --------
#define MACON3_PADCFG2  (1<<7)
#define MACON3_PADCFG1  (1<<6)
#define MACON3_PADCFG0  (1<<5)
#define MACON3_TXCRCEN  (1<<4)
#define MACON3_PHDREN   (1<<3)
#define MACON3_HFRMEN   (1<<2)
#define MACON3_FRMLNEN  (1<<1)
#define MACON3_FULDPX   (1)
        
// MACON4 bits --------
#define MACON4_DEFER    (1<<6)
        
// MICMD bits ---------
#define MICMD_MIISCAN   (1<<1)
#define MICMD_MIIRD             (1)

// MISTAT bits --------
#define MISTAT_NVALID   (1<<2)
#define MISTAT_SCAN             (1<<1)
#define MISTAT_BUSY             (1)
        
// EFLOCON bits -----
#define EFLOCON_FCEN1   (1<<1)
#define EFLOCON_FCEN0   (1)


// PHY bits

// PHCON1 bits ----------
#define PHCON1_PDPXMD   (1ul<<8)

// PHSTAT1 bits --------
#define PHSTAT1_LLSTAT  (1ul<<2)

// PHCON2 bits ----------
#define PHCON2_FRCLNK   (1ul<<14)
#define PHCON2_HDLDIS   (1ul<<8)
#define PHCON2_RXAPDIS  (1ul<<4)

// PHSTAT2 bits --------
#define PHSTAT2_TXSTAT  (1ul<<13)
#define PHSTAT2_RXSTAT  (1ul<<12)
#define PHSTAT2_COLSTAT (1ul<<11)
#define PHSTAT2_LSTAT   (1ul<<10)

// PHIE bits -----------
#define PHIE_PLNKIE             (1ul<<4)
#define PHIE_PGEIE              (1ul<<1)

// PHIR bits -----------
#define PHIR_PLNKIF             (1ul<<4)
#define PHIR_PGIF               (1ul<<2)

// PHLCON bits -------
#define PHLCON_LACFG3   (1ul<<11)
#define PHLCON_LACFG2   (1ul<<10)
#define PHLCON_LACFG1   (1ul<<9)
#define PHLCON_LACFG0   (1ul<<8)
#define PHLCON_LBCFG3   (1ul<<7)
#define PHLCON_LBCFG2   (1ul<<6)
#define PHLCON_LBCFG1   (1ul<<5)
#define PHLCON_LBCFG0   (1ul<<4)
#define PHLCON_LFRQ1    (1ul<<3)
#define PHLCON_LFRQ0    (1ul<<2)
#define PHLCON_STRCH    (1ul<<1)

#endif
1	hedin	15	/*********************************************************************
2			*
3			* Ethernet registers/bits for PIC18F97J60
4			*
5			*********************************************************************
6			* FileName: ETH97J60.h
7			* Description: Include file for Ethernet related data structures
8			* constants.
9			* Company: Microchip Technology, Inc.
10			*
11			* Software License Agreement
12			*
13			* Copyright © 2002-2007 Microchip Technology Inc. All rights
14			* reserved.
15			*
16			* Microchip licenses to you the right to use, modify, copy, and
17			* distribute:
18			* (i) the Software when embedded on a Microchip microcontroller or
19			* digital signal controller product (“Device”) which is
20			* integrated into Licensee’s product; or
21			* (ii) ONLY the Software driver source files ENC28J60.c and
22			* ENC28J60.h ported to a non-Microchip device used in
23			* conjunction with a Microchip ethernet controller for the
24			* sole purpose of interfacing with the ethernet controller.
25			*
26			* You should refer to the license agreement accompanying this
27			* Software for additional information regarding your rights and
28			* obligations.
29			*
30			* THE SOFTWARE AND DOCUMENTATION ARE PROVIDED “AS IS” WITHOUT
31			* WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT
32			* LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A
33			* PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL
34			* MICROCHIP BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR
35			* CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF
36			* PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
37			* BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE
38			* THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER
39			* SIMILAR COSTS, WHETHER ASSERTED ON THE BASIS OF CONTRACT, TORT
40			* (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR OTHERWISE.
41			*
42			*
43			* Author Date Comment
44			*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
45			* Howard Schlunder 06/12/05 Modified for 97J60 (from ENC28J60)
46			* Howard Schlunder 03/23/06 Updated for Advance Data Sheet
47			* Howard Schlunder 06/29/06 Changed MACON3_PHDRLEN to MACON3_PHDREN
48			* Howard Schlunder 09/13/06 Removed a lot of bits for
49			* preliminary data sheet, added RXAPDIS
50			********************************************************************/
51
52			#ifndef __ETH97J60_H
53			#define __ETH97J60_H
54			#include "GenericTypeDefs.h"
55
56			typedef union {
57			BYTE v[7];
58			struct {
59			WORD ByteCount;
60			unsigned CollisionCount:4;
61			unsigned CRCError:1;
62			unsigned LengthCheckError:1;
63			unsigned LengthOutOfRange:1;
64			unsigned Done:1;
65			unsigned Multicast:1;
66			unsigned Broadcast:1;
67			unsigned PacketDefer:1;
68			unsigned ExcessiveDefer:1;
69			unsigned MaximumCollisions:1;
70			unsigned LateCollision:1;
71			unsigned Giant:1;
72			unsigned Underrun:1;
73			WORD BytesTransmittedOnWire;
74			unsigned ControlFrame:1;
75			unsigned PAUSEControlFrame:1;
76			unsigned BackpressureApplied:1;
77			unsigned VLANTaggedFrame:1;
78			unsigned Zeros:4;
79			} bits;
80			} TXSTATUS;
81
82			typedef union {
83			BYTE v[4];
84			struct {
85			WORD ByteCount;
86			unsigned PreviouslyIgnored:1;
87			unsigned RXDCPreviouslySeen:1;
88			unsigned CarrierPreviouslySeen:1;
89			unsigned CodeViolation:1;
90			unsigned CRCError:1;
91			unsigned LengthCheckError:1;
92			unsigned LengthOutOfRange:1;
93			unsigned ReceiveOk:1;
94			unsigned Multicast:1;
95			unsigned Broadcast:1;
96			unsigned DribbleNibble:1;
97			unsigned ControlFrame:1;
98			unsigned PauseControlFrame:1;
99			unsigned UnsupportedOpcode:1;
100			unsigned VLANType:1;
101			unsigned Zero:1;
102			} bits;
103			} RXSTATUS;
104
105
106
107			/******************************************************************************
108			* PHY Register Locations
109			******************************************************************************/
110			#define PHCON1 0x00
111			#define PHSTAT1 0x01
112			#define PHCON2 0x10
113			#define PHSTAT2 0x11
114			#define PHIE 0x12
115			#define PHIR 0x13
116			#define PHLCON 0x14
117
118
119			typedef union {
120			WORD Val;
121			WORD_VAL VAL;
122
123			// PHCON1 bits ----------
124			struct {
125			unsigned :8;
126			unsigned PDPXMD:1;
127			unsigned :7;
128			} PHCON1bits;
129
130			// PHSTAT1 bits --------
131			struct {
132			unsigned :2;
133			unsigned LLSTAT:1;
134			unsigned :5;
135			unsigned :8;
136			} PHSTAT1bits;
137
138			// PHCON2 bits ----------
139			struct {
140			unsigned :4;
141			unsigned RXAPDIS:1;
142			unsigned :3;
143			unsigned HDLDIS:1;
144			unsigned :5;
145			unsigned FRCLNK:1;
146			unsigned :1;
147			} PHCON2bits;
148
149			// PHSTAT2 bits --------
150			struct {
151			unsigned :8;
152			unsigned :2;
153			unsigned LSTAT:1;
154			unsigned COLSTAT:1;
155			unsigned RXSTAT:1;
156			unsigned TXSTAT:1;
157			unsigned :2;
158			} PHSTAT2bits;
159
160			// PHIE bits -----------
161			struct {
162			unsigned :1;
163			unsigned PGEIE:1;
164			unsigned :2;
165			unsigned PLNKIE:1;
166			unsigned :3;
167			unsigned :8;
168			} PHIEbits;
169
170			// PHIR bits -----------
171			struct {
172			unsigned :2;
173			unsigned PGIF:1;
174			unsigned :1;
175			unsigned PLNKIF:1;
176			unsigned :3;
177			unsigned :8;
178			} PHIRbits;
179
180			// PHLCON bits -------
181			struct {
182			unsigned :1;
183			unsigned STRCH:1;
184			unsigned LFRQ0:1;
185			unsigned LFRQ1:1;
186			unsigned LBCFG0:1;
187			unsigned LBCFG1:1;
188			unsigned LBCFG2:1;
189			unsigned LBCFG3:1;
190			unsigned LACFG0:1;
191			unsigned LACFG1:1;
192			unsigned LACFG2:1;
193			unsigned LACFG3:1;
194			unsigned :4;
195			} PHLCONbits;
196			struct {
197			unsigned :1;
198			unsigned STRCH:1;
199			unsigned LFRQ:2;
200			unsigned LBCFG:4;
201			unsigned LACFG:4;
202			unsigned :4;
203			} PHLCONbits2;
204			} PHYREG;
205
206
207			/******************************************************************************
208			* Individual Register Bits
209			******************************************************************************/
210			// ETH/MAC/MII bits
211
212			// EIE bits ----------
213			#define EIE_PKTIE (1<<6)
214			#define EIE_DMAIE (1<<5)
215			#define EIE_LINKIE (1<<4)
216			#define EIE_TXIE (1<<3)
217			#define EIE_TXERIE (1<<1)
218			#define EIE_RXERIE (1)
219
220			// EIR bits ----------
221			#define EIR_PKTIF (1<<6)
222			#define EIR_DMAIF (1<<5)
223			#define EIR_LINKIF (1<<4)
224			#define EIR_TXIF (1<<3)
225			#define EIR_TXERIF (1<<1)
226			#define EIR_RXERIF (1)
227
228			// ESTAT bits ---------
229			#define ESTAT_BUFER (1<<6)
230			#define ESTAT_RXBUSY (1<<2)
231			#define ESTAT_TXABRT (1<<1)
232			#define ESTAT_PHYRDY (1)
233
234			// ECON2 bits --------
235			#define ECON2_AUTOINC (1<<7)
236			#define ECON2_PKTDEC (1<<6)
237			#define ECON2_ETHEN (1<<5)
238
239			// ECON1 bits --------
240			#define ECON1_TXRST (1<<7)
241			#define ECON1_RXRST (1<<6)
242			#define ECON1_DMAST (1<<5)
243			#define ECON1_CSUMEN (1<<4)
244			#define ECON1_TXRTS (1<<3)
245			#define ECON1_RXEN (1<<2)
246
247			// ERXFCON bits ------
248			#define ERXFCON_UCEN (1<<7)
249			#define ERXFCON_ANDOR (1<<6)
250			#define ERXFCON_CRCEN (1<<5)
251			#define ERXFCON_PMEN (1<<4)
252			#define ERXFCON_MPEN (1<<3)
253			#define ERXFCON_HTEN (1<<2)
254			#define ERXFCON_MCEN (1<<1)
255			#define ERXFCON_BCEN (1)
256
257			// MACON1 bits --------
258			#define MACON1_TXPAUS (1<<3)
259			#define MACON1_RXPAUS (1<<2)
260			#define MACON1_PASSALL (1<<1)
261			#define MACON1_MARXEN (1)
262
263			// MACON3 bits --------
264			#define MACON3_PADCFG2 (1<<7)
265			#define MACON3_PADCFG1 (1<<6)
266			#define MACON3_PADCFG0 (1<<5)
267			#define MACON3_TXCRCEN (1<<4)
268			#define MACON3_PHDREN (1<<3)
269			#define MACON3_HFRMEN (1<<2)
270			#define MACON3_FRMLNEN (1<<1)
271			#define MACON3_FULDPX (1)
272
273			// MACON4 bits --------
274			#define MACON4_DEFER (1<<6)
275
276			// MICMD bits ---------
277			#define MICMD_MIISCAN (1<<1)
278			#define MICMD_MIIRD (1)
279
280			// MISTAT bits --------
281			#define MISTAT_NVALID (1<<2)
282			#define MISTAT_SCAN (1<<1)
283			#define MISTAT_BUSY (1)
284
285			// EFLOCON bits -----
286			#define EFLOCON_FCEN1 (1<<1)
287			#define EFLOCON_FCEN0 (1)
288
289
290
291			// PHY bits
292
293			// PHCON1 bits ----------
294			#define PHCON1_PDPXMD (1ul<<8)
295
296			// PHSTAT1 bits --------
297			#define PHSTAT1_LLSTAT (1ul<<2)
298
299			// PHCON2 bits ----------
300			#define PHCON2_FRCLNK (1ul<<14)
301			#define PHCON2_HDLDIS (1ul<<8)
302			#define PHCON2_RXAPDIS (1ul<<4)
303
304			// PHSTAT2 bits --------
305			#define PHSTAT2_TXSTAT (1ul<<13)
306			#define PHSTAT2_RXSTAT (1ul<<12)
307			#define PHSTAT2_COLSTAT (1ul<<11)
308			#define PHSTAT2_LSTAT (1ul<<10)
309
310			// PHIE bits -----------
311			#define PHIE_PLNKIE (1ul<<4)
312			#define PHIE_PGEIE (1ul<<1)
313
314			// PHIR bits -----------
315			#define PHIR_PLNKIF (1ul<<4)
316			#define PHIR_PGIF (1ul<<2)
317
318			// PHLCON bits -------
319			#define PHLCON_LACFG3 (1ul<<11)
320			#define PHLCON_LACFG2 (1ul<<10)
321			#define PHLCON_LACFG1 (1ul<<9)
322			#define PHLCON_LACFG0 (1ul<<8)
323			#define PHLCON_LBCFG3 (1ul<<7)
324			#define PHLCON_LBCFG2 (1ul<<6)
325			#define PHLCON_LBCFG1 (1ul<<5)
326			#define PHLCON_LBCFG0 (1ul<<4)
327			#define PHLCON_LFRQ1 (1ul<<3)
328			#define PHLCON_LFRQ0 (1ul<<2)
329			#define PHLCON_STRCH (1ul<<1)
330
331			#endif