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/*********************************************************************
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*
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* ENC28J60 registers/bits
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*
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*********************************************************************
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* FileName: ENC28J60.h
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* Description: Include file for ENC28J60 control registers
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* Company: Microchip Technology, Inc.
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*
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* Software License Agreement
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*
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* Copyright © 2002-2007 Microchip Technology Inc. All rights
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* reserved.
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*
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* Microchip licenses to you the right to use, modify, copy, and
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* distribute:
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* (i) the Software when embedded on a Microchip microcontroller or
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* digital signal controller product (“Device”) which is
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* integrated into Licensee’s product; or
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* (ii) ONLY the Software driver source files ENC28J60.c and
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* ENC28J60.h ported to a non-Microchip device used in
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* conjunction with a Microchip ethernet controller for the
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* sole purpose of interfacing with the ethernet controller.
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*
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* You should refer to the license agreement accompanying this
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* Software for additional information regarding your rights and
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* obligations.
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*
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* THE SOFTWARE AND DOCUMENTATION ARE PROVIDED “AS IS” WITHOUT
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* WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT
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* LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A
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* PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* MICROCHIP BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF
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* PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
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* BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE
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* THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER
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* SIMILAR COSTS, WHETHER ASSERTED ON THE BASIS OF CONTRACT, TORT
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* (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR OTHERWISE.
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*
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*
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* Author Date Comment
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*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* Howard Schlunder 06/01/04 Original
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* Howard Schlunder 06/29/04 Fixed byte boundary problems on a
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* couple of PHY register structs.
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* Howard Schlunder 09/29/04 Matched with data sheet
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* Howard Schlunder 01/04/06 Matched with new data sheet
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* Howard Schlunder 06/29/06 Changed MACON3.PHDRLEN to PHDREN
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* Howard Schlunder 07/21/06 Several bits removed to match now
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* reserved bits in rev. B data sheet
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* (DS39662B)
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********************************************************************/
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#ifndef __ENC28J60_H
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#define __ENC28J60_H
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#include "GenericTypeDefs.h"
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typedef union {
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BYTE v[7];
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struct {
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WORD ByteCount;
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unsigned char CollisionCount:4;
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unsigned char CRCError:1;
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unsigned char LengthCheckError:1;
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unsigned char LengthOutOfRange:1;
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unsigned char Done:1;
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unsigned char Multicast:1;
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unsigned char Broadcast:1;
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unsigned char PacketDefer:1;
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unsigned char ExcessiveDefer:1;
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unsigned char MaximumCollisions:1;
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unsigned char LateCollision:1;
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unsigned char Giant:1;
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unsigned char Underrun:1;
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WORD BytesTransmittedOnWire;
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unsigned char ControlFrame:1;
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unsigned char PAUSEControlFrame:1;
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unsigned char BackpressureApplied:1;
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unsigned char VLANTaggedFrame:1;
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unsigned char Zeros:4;
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} bits;
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} TXSTATUS;
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typedef union {
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BYTE v[4];
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struct {
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WORD ByteCount;
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unsigned char PreviouslyIgnored:1;
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unsigned char RXDCPreviouslySeen:1;
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unsigned char CarrierPreviouslySeen:1;
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unsigned char CodeViolation:1;
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unsigned char CRCError:1;
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unsigned char LengthCheckError:1;
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unsigned char LengthOutOfRange:1;
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unsigned char ReceiveOk:1;
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unsigned char Multicast:1;
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unsigned char Broadcast:1;
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unsigned char DribbleNibble:1;
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unsigned char ControlFrame:1;
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unsigned char PauseControlFrame:1;
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unsigned char UnsupportedOpcode:1;
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unsigned char VLANType:1;
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unsigned char Zero:1;
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} bits;
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} RXSTATUS;
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/******************************************************************************
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* Register locations
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******************************************************************************/
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// Bank 0 registers --------
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#define ERDPTL 0x00
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#define ERDPTH 0x01
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#define EWRPTL 0x02
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#define EWRPTH 0x03
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#define ETXSTL 0x04
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#define ETXSTH 0x05
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#define ETXNDL 0x06
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#define ETXNDH 0x07
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#define ERXSTL 0x08
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#define ERXSTH 0x09
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#define ERXNDL 0x0A
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#define ERXNDH 0x0B
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#define ERXRDPTL 0x0C
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#define ERXRDPTH 0x0D
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#define ERXWRPTL 0x0E
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#define ERXWRPTH 0x0F
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#define EDMASTL 0x10
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#define EDMASTH 0x11
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#define EDMANDL 0x12
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#define EDMANDH 0x13
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#define EDMADSTL 0x14
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#define EDMADSTH 0x15
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#define EDMACSL 0x16
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#define EDMACSH 0x17
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//#define 0x18
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//#define 0x19
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//#define r 0x1A
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#define EIE 0x1B
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#define EIR 0x1C
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#define ESTAT 0x1D
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#define ECON2 0x1E
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#define ECON1 0x1F
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// Bank 1 registers -----
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#define EHT0 0x100
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#define EHT1 0x101
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#define EHT2 0x102
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#define EHT3 0x103
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#define EHT4 0x104
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#define EHT5 0x105
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#define EHT6 0x106
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#define EHT7 0x107
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#define EPMM0 0x108
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#define EPMM1 0x109
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#define EPMM2 0x10A
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#define EPMM3 0x10B
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#define EPMM4 0x10C
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#define EPMM5 0x10D
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#define EPMM6 0x10E
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#define EPMM7 0x10F
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#define EPMCSL 0x110
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#define EPMCSH 0x111
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//#define 0x112
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//#define 0x113
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#define EPMOL 0x114
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#define EPMOH 0x115
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//#define r 0x116
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//#define r 0x117
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#define ERXFCON 0x118
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#define EPKTCNT 0x119
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//#define r 0x11A
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//#define EIE 0x11B
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//#define EIR 0x11C
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//#define ESTAT 0x11D
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//#define ECON2 0x11E
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//#define ECON1 0x11F
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// Bank 2 registers -----
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#define MACON1 0x200
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//#define r 0x201
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#define MACON3 0x202
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#define MACON4 0x203
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#define MABBIPG 0x204
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//#define 0x205
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#define MAIPGL 0x206
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#define MAIPGH 0x207
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#define MACLCON1 0x208
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#define MACLCON2 0x209
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#define MAMXFLL 0x20A
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#define MAMXFLH 0x20B
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//#define r 0x20C
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//#define r 0x20D
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//#define r 0x20E
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//#define 0x20F
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//#define r 0x210
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//#define r 0x211
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#define MICMD 0x212
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//#define r 0x213
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#define MIREGADR 0x214
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//#define r 0x215
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#define MIWRL 0x216
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#define MIWRH 0x217
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#define MIRDL 0x218
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#define MIRDH 0x219
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//#define r 0x21A
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//#define EIE 0x21B
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//#define EIR 0x21C
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//#define ESTAT 0x21D
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//#define ECON2 0x21E
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//#define ECON1 0x21F
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// Bank 3 registers -----
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#define MAADR5 0x300
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#define MAADR6 0x301
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#define MAADR3 0x302
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#define MAADR4 0x303
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#define MAADR1 0x304
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#define MAADR2 0x305
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#define EBSTSD 0x306
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#define EBSTCON 0x307
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#define EBSTCSL 0x308
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#define EBSTCSH 0x309
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#define MISTAT 0x30A
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//#define 0x30B
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//#define 0x30C
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//#define 0x30D
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//#define 0x30E
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//#define 0x30F
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//#define 0x310
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//#define 0x311
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#define EREVID 0x312
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//#define 0x313
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//#define 0x314
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#define ECOCON 0x315
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//#define 0x316
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#define EFLOCON 0x317
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#define EPAUSL 0x318
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#define EPAUSH 0x319
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//#define r 0x31A
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//#define EIE 0x31B
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//#define EIR 0x31C
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//#define ESTAT 0x31D
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//#define ECON2 0x31E
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//#define ECON1 0x31F
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// Structures
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typedef union _REG
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{
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BYTE Val;
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// EIE bits ----------
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struct {
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unsigned char RXERIE:1;
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unsigned char TXERIE:1;
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unsigned char :1;
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unsigned char TXIE:1;
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unsigned char LINKIE:1;
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unsigned char DMAIE:1;
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| 262 |
unsigned char PKTIE:1;
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unsigned char INTIE:1;
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} EIEbits;
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// EIR bits ----------
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struct {
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unsigned char RXERIF:1;
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unsigned char TXERIF:1;
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unsigned char :1;
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| 271 |
unsigned char TXIF:1;
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| 272 |
unsigned char LINKIF:1;
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unsigned char DMAIF:1;
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unsigned char PKTIF:1;
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| 275 |
unsigned char :1;
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} EIRbits;
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// ESTAT bits ---------
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struct {
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unsigned char CLKRDY:1;
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unsigned char TXABRT:1;
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| 282 |
unsigned char RXBUSY:1;
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| 283 |
unsigned char :1;
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unsigned char LATECOL:1;
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unsigned char :1;
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| 286 |
unsigned char BUFER:1;
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| 287 |
unsigned char INT:1;
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| 288 |
} ESTATbits;
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| 290 |
// ECON2 bits --------
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struct {
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unsigned char :3;
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unsigned char VRPS:1;
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unsigned char :1;
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| 295 |
unsigned char PWRSV:1;
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| 296 |
unsigned char PKTDEC:1;
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| 297 |
unsigned char AUTOINC:1;
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} ECON2bits;
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// ECON1 bits --------
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struct {
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unsigned char BSEL0:1;
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unsigned char BSEL1:1;
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unsigned char RXEN:1;
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unsigned char TXRTS:1;
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| 306 |
unsigned char CSUMEN:1;
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unsigned char DMAST:1;
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| 308 |
unsigned char RXRST:1;
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| 309 |
unsigned char TXRST:1;
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} ECON1bits;
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// ERXFCON bits ------
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struct {
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unsigned char BCEN:1;
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unsigned char MCEN:1;
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| 316 |
unsigned char HTEN:1;
|
| 317 |
unsigned char MPEN:1;
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| 318 |
unsigned char PMEN:1;
|
| 319 |
unsigned char CRCEN:1;
|
| 320 |
unsigned char ANDOR:1;
|
| 321 |
unsigned char UCEN:1;
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| 322 |
} ERXFCONbits;
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|
| 324 |
// MACON1 bits --------
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struct {
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| 326 |
unsigned char MARXEN:1;
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| 327 |
unsigned char PASSALL:1;
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| 328 |
unsigned char RXPAUS:1;
|
| 329 |
unsigned char TXPAUS:1;
|
| 330 |
unsigned char :4;
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| 331 |
} MACON1bits;
|
| 332 |
|
| 333 |
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| 334 |
// MACON3 bits --------
|
| 335 |
struct {
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| 336 |
unsigned char FULDPX:1;
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| 337 |
unsigned char FRMLNEN:1;
|
| 338 |
unsigned char HFRMEN:1;
|
| 339 |
unsigned char PHDREN:1;
|
| 340 |
unsigned char TXCRCEN:1;
|
| 341 |
unsigned char PADCFG0:1;
|
| 342 |
unsigned char PADCFG1:1;
|
| 343 |
unsigned char PADCFG2:1;
|
| 344 |
} MACON3bits;
|
| 345 |
struct {
|
| 346 |
unsigned char FULDPX:1;
|
| 347 |
unsigned char FRMLNEN:1;
|
| 348 |
unsigned char HFRMEN:1;
|
| 349 |
unsigned char PHDREN:1;
|
| 350 |
unsigned char TXCRCEN:1;
|
| 351 |
unsigned char PADCFG:3;
|
| 352 |
} MACON3bits2;
|
| 353 |
|
| 354 |
// MACON4 bits --------
|
| 355 |
struct {
|
| 356 |
unsigned char :4;
|
| 357 |
unsigned char NOBKOFF:1;
|
| 358 |
unsigned char BPEN:1;
|
| 359 |
unsigned char DEFER:1;
|
| 360 |
unsigned char :1;
|
| 361 |
} MACON4bits;
|
| 362 |
|
| 363 |
// MICMD bits ---------
|
| 364 |
struct {
|
| 365 |
unsigned char MIIRD:1;
|
| 366 |
unsigned char MIISCAN:1;
|
| 367 |
unsigned char :6;
|
| 368 |
} MICMDbits;
|
| 369 |
|
| 370 |
// EBSTCON bits -----
|
| 371 |
struct {
|
| 372 |
unsigned char BISTST:1;
|
| 373 |
unsigned char TME:1;
|
| 374 |
unsigned char TMSEL0:1;
|
| 375 |
unsigned char TMSEL1:1;
|
| 376 |
unsigned char PSEL:1;
|
| 377 |
unsigned char PSV0:1;
|
| 378 |
unsigned char PSV1:1;
|
| 379 |
unsigned char PSV2:1;
|
| 380 |
} EBSTCONbits;
|
| 381 |
struct {
|
| 382 |
unsigned char BISTST:1;
|
| 383 |
unsigned char TME:1;
|
| 384 |
unsigned char TMSEL:2;
|
| 385 |
unsigned char PSEL:1;
|
| 386 |
unsigned char PSV:3;
|
| 387 |
} EBSTCONbits2;
|
| 388 |
|
| 389 |
// MISTAT bits --------
|
| 390 |
struct {
|
| 391 |
unsigned char BUSY:1;
|
| 392 |
unsigned char SCAN:1;
|
| 393 |
unsigned char NVALID:1;
|
| 394 |
unsigned char :5;
|
| 395 |
} MISTATbits;
|
| 396 |
|
| 397 |
// ECOCON bits -------
|
| 398 |
struct {
|
| 399 |
unsigned char COCON0:1;
|
| 400 |
unsigned char COCON1:1;
|
| 401 |
unsigned char COCON2:1;
|
| 402 |
unsigned char :5;
|
| 403 |
} ECOCONbits;
|
| 404 |
struct {
|
| 405 |
unsigned char COCON:3;
|
| 406 |
unsigned char :5;
|
| 407 |
} ECOCONbits2;
|
| 408 |
|
| 409 |
// EFLOCON bits -----
|
| 410 |
struct {
|
| 411 |
unsigned char FCEN0:1;
|
| 412 |
unsigned char FCEN1:1;
|
| 413 |
unsigned char FULDPXS:1;
|
| 414 |
unsigned char :5;
|
| 415 |
} EFLOCONbits;
|
| 416 |
struct {
|
| 417 |
unsigned char FCEN:2;
|
| 418 |
unsigned char FULDPXS:1;
|
| 419 |
unsigned char :5;
|
| 420 |
} EFLOCONbits2;
|
| 421 |
} REG;
|
| 422 |
|
| 423 |
|
| 424 |
/******************************************************************************
|
| 425 |
* PH Register Locations
|
| 426 |
******************************************************************************/
|
| 427 |
#define PHCON1 0x00
|
| 428 |
#define PHSTAT1 0x01
|
| 429 |
#define PHID1 0x02
|
| 430 |
#define PHID2 0x03
|
| 431 |
#define PHCON2 0x10
|
| 432 |
#define PHSTAT2 0x11
|
| 433 |
#define PHIE 0x12
|
| 434 |
#define PHIR 0x13
|
| 435 |
#define PHLCON 0x14
|
| 436 |
|
| 437 |
|
| 438 |
typedef union {
|
| 439 |
WORD Val;
|
| 440 |
WORD_VAL VAL;
|
| 441 |
|
| 442 |
// PHCON1 bits ----------
|
| 443 |
struct {
|
| 444 |
unsigned :8;
|
| 445 |
unsigned PDPXMD:1;
|
| 446 |
unsigned :2;
|
| 447 |
unsigned PPWRSV:1;
|
| 448 |
unsigned :2;
|
| 449 |
unsigned PLOOPBK:1;
|
| 450 |
unsigned PRST:1;
|
| 451 |
} PHCON1bits;
|
| 452 |
|
| 453 |
// PHSTAT1 bits --------
|
| 454 |
struct {
|
| 455 |
unsigned :1;
|
| 456 |
unsigned JBSTAT:1;
|
| 457 |
unsigned LLSTAT:1;
|
| 458 |
unsigned :5;
|
| 459 |
unsigned :3;
|
| 460 |
unsigned PHDPX:1;
|
| 461 |
unsigned PFDPX:1;
|
| 462 |
unsigned :3;
|
| 463 |
} PHSTAT1bits;
|
| 464 |
|
| 465 |
// PHID2 bits ----------
|
| 466 |
struct {
|
| 467 |
unsigned PREV0:1;
|
| 468 |
unsigned PREV1:1;
|
| 469 |
unsigned PREV2:1;
|
| 470 |
unsigned PREV3:1;
|
| 471 |
unsigned PPN0:1;
|
| 472 |
unsigned PPN1:1;
|
| 473 |
unsigned PPN2:1;
|
| 474 |
unsigned PPN3:1;
|
| 475 |
unsigned PPN4:1;
|
| 476 |
unsigned PPN5:1;
|
| 477 |
unsigned PID19:1;
|
| 478 |
unsigned PID20:1;
|
| 479 |
unsigned PID21:1;
|
| 480 |
unsigned PID22:1;
|
| 481 |
unsigned PID23:1;
|
| 482 |
unsigned PID24:1;
|
| 483 |
} PHID2bits;
|
| 484 |
struct {
|
| 485 |
unsigned PREV:4;
|
| 486 |
unsigned PPNL:4;
|
| 487 |
unsigned PPNH:2;
|
| 488 |
unsigned PID:6;
|
| 489 |
} PHID2bits2;
|
| 490 |
|
| 491 |
// PHCON2 bits ----------
|
| 492 |
struct {
|
| 493 |
unsigned :8;
|
| 494 |
unsigned HDLDIS:1;
|
| 495 |
unsigned :1;
|
| 496 |
unsigned JABBER:1;
|
| 497 |
unsigned :2;
|
| 498 |
unsigned TXDIS:1;
|
| 499 |
unsigned FRCLNK:1;
|
| 500 |
unsigned :1;
|
| 501 |
} PHCON2bits;
|
| 502 |
|
| 503 |
// PHSTAT2 bits --------
|
| 504 |
struct {
|
| 505 |
unsigned :5;
|
| 506 |
unsigned PLRITY:1;
|
| 507 |
unsigned :2;
|
| 508 |
unsigned :1;
|
| 509 |
unsigned DPXSTAT:1;
|
| 510 |
unsigned LSTAT:1;
|
| 511 |
unsigned COLSTAT:1;
|
| 512 |
unsigned RXSTAT:1;
|
| 513 |
unsigned TXSTAT:1;
|
| 514 |
unsigned :2;
|
| 515 |
} PHSTAT2bits;
|
| 516 |
|
| 517 |
// PHIE bits -----------
|
| 518 |
struct {
|
| 519 |
unsigned :1;
|
| 520 |
unsigned PGEIE:1;
|
| 521 |
unsigned :2;
|
| 522 |
unsigned PLNKIE:1;
|
| 523 |
unsigned :3;
|
| 524 |
unsigned :8;
|
| 525 |
} PHIEbits;
|
| 526 |
|
| 527 |
// PHIR bits -----------
|
| 528 |
struct {
|
| 529 |
unsigned :2;
|
| 530 |
unsigned PGIF:1;
|
| 531 |
unsigned :1;
|
| 532 |
unsigned PLNKIF:1;
|
| 533 |
unsigned :3;
|
| 534 |
unsigned :8;
|
| 535 |
} PHIRbits;
|
| 536 |
|
| 537 |
// PHLCON bits -------
|
| 538 |
struct {
|
| 539 |
unsigned :1;
|
| 540 |
unsigned STRCH:1;
|
| 541 |
unsigned LFRQ0:1;
|
| 542 |
unsigned LFRQ1:1;
|
| 543 |
unsigned LBCFG0:1;
|
| 544 |
unsigned LBCFG1:1;
|
| 545 |
unsigned LBCFG2:1;
|
| 546 |
unsigned LBCFG3:1;
|
| 547 |
unsigned LACFG0:1;
|
| 548 |
unsigned LACFG1:1;
|
| 549 |
unsigned LACFG2:1;
|
| 550 |
unsigned LACFG3:1;
|
| 551 |
unsigned :4;
|
| 552 |
} PHLCONbits;
|
| 553 |
struct {
|
| 554 |
unsigned :1;
|
| 555 |
unsigned STRCH:1;
|
| 556 |
unsigned LFRQ:2;
|
| 557 |
unsigned LBCFG:4;
|
| 558 |
unsigned LACFG:4;
|
| 559 |
unsigned :4;
|
| 560 |
} PHLCONbits2;
|
| 561 |
} PHYREG;
|
| 562 |
|
| 563 |
|
| 564 |
/******************************************************************************
|
| 565 |
* Individual Register Bits
|
| 566 |
******************************************************************************/
|
| 567 |
// ETH/MAC/MII bits
|
| 568 |
|
| 569 |
// EIE bits ----------
|
| 570 |
#define EIE_INTIE (1<<7)
|
| 571 |
#define EIE_PKTIE (1<<6)
|
| 572 |
#define EIE_DMAIE (1<<5)
|
| 573 |
#define EIE_LINKIE (1<<4)
|
| 574 |
#define EIE_TXIE (1<<3)
|
| 575 |
#define EIE_TXERIE (1<<1)
|
| 576 |
#define EIE_RXERIE (1)
|
| 577 |
|
| 578 |
// EIR bits ----------
|
| 579 |
#define EIR_PKTIF (1<<6)
|
| 580 |
#define EIR_DMAIF (1<<5)
|
| 581 |
#define EIR_LINKIF (1<<4)
|
| 582 |
#define EIR_TXIF (1<<3)
|
| 583 |
#define EIR_TXERIF (1<<1)
|
| 584 |
#define EIR_RXERIF (1)
|
| 585 |
|
| 586 |
// ESTAT bits ---------
|
| 587 |
#define ESTAT_INT (1<<7)
|
| 588 |
#define ESTAT_BUFER (1<<6)
|
| 589 |
#define ESTAT_LATECOL (1<<4)
|
| 590 |
#define ESTAT_RXBUSY (1<<2)
|
| 591 |
#define ESTAT_TXABRT (1<<1)
|
| 592 |
#define ESTAT_CLKRDY (1)
|
| 593 |
|
| 594 |
// ECON2 bits --------
|
| 595 |
#define ECON2_AUTOINC (1<<7)
|
| 596 |
#define ECON2_PKTDEC (1<<6)
|
| 597 |
#define ECON2_PWRSV (1<<5)
|
| 598 |
#define ECON2_VRPS (1<<3)
|
| 599 |
|
| 600 |
// ECON1 bits --------
|
| 601 |
#define ECON1_TXRST (1<<7)
|
| 602 |
#define ECON1_RXRST (1<<6)
|
| 603 |
#define ECON1_DMAST (1<<5)
|
| 604 |
#define ECON1_CSUMEN (1<<4)
|
| 605 |
#define ECON1_TXRTS (1<<3)
|
| 606 |
#define ECON1_RXEN (1<<2)
|
| 607 |
#define ECON1_BSEL1 (1<<1)
|
| 608 |
#define ECON1_BSEL0 (1)
|
| 609 |
|
| 610 |
// ERXFCON bits ------
|
| 611 |
#define ERXFCON_UCEN (1<<7)
|
| 612 |
#define ERXFCON_ANDOR (1<<6)
|
| 613 |
#define ERXFCON_CRCEN (1<<5)
|
| 614 |
#define ERXFCON_PMEN (1<<4)
|
| 615 |
#define ERXFCON_MPEN (1<<3)
|
| 616 |
#define ERXFCON_HTEN (1<<2)
|
| 617 |
#define ERXFCON_MCEN (1<<1)
|
| 618 |
#define ERXFCON_BCEN (1)
|
| 619 |
|
| 620 |
// MACON1 bits --------
|
| 621 |
#define MACON1_TXPAUS (1<<3)
|
| 622 |
#define MACON1_RXPAUS (1<<2)
|
| 623 |
#define MACON1_PASSALL (1<<1)
|
| 624 |
#define MACON1_MARXEN (1)
|
| 625 |
|
| 626 |
// MACON3 bits --------
|
| 627 |
#define MACON3_PADCFG2 (1<<7)
|
| 628 |
#define MACON3_PADCFG1 (1<<6)
|
| 629 |
#define MACON3_PADCFG0 (1<<5)
|
| 630 |
#define MACON3_TXCRCEN (1<<4)
|
| 631 |
#define MACON3_PHDREN (1<<3)
|
| 632 |
#define MACON3_HFRMEN (1<<2)
|
| 633 |
#define MACON3_FRMLNEN (1<<1)
|
| 634 |
#define MACON3_FULDPX (1)
|
| 635 |
|
| 636 |
// MACON4 bits --------
|
| 637 |
#define MACON4_DEFER (1<<6)
|
| 638 |
#define MACON4_BPEN (1<<5)
|
| 639 |
#define MACON4_NOBKOFF (1<<4)
|
| 640 |
|
| 641 |
// MICMD bits ---------
|
| 642 |
#define MICMD_MIISCAN (1<<1)
|
| 643 |
#define MICMD_MIIRD (1)
|
| 644 |
|
| 645 |
// EBSTCON bits -----
|
| 646 |
#define EBSTCON_PSV2 (1<<7)
|
| 647 |
#define EBSTCON_PSV1 (1<<6)
|
| 648 |
#define EBSTCON_PSV0 (1<<5)
|
| 649 |
#define EBSTCON_PSEL (1<<4)
|
| 650 |
#define EBSTCON_TMSEL1 (1<<3)
|
| 651 |
#define EBSTCON_TMSEL0 (1<<2)
|
| 652 |
#define EBSTCON_TME (1<<1)
|
| 653 |
#define EBSTCON_BISTST (1)
|
| 654 |
|
| 655 |
// MISTAT bits --------
|
| 656 |
#define MISTAT_NVALID (1<<2)
|
| 657 |
#define MISTAT_SCAN (1<<1)
|
| 658 |
#define MISTAT_BUSY (1)
|
| 659 |
|
| 660 |
// ECOCON bits -------
|
| 661 |
#define ECOCON_COCON2 (1<<2)
|
| 662 |
#define ECOCON_COCON1 (1<<1)
|
| 663 |
#define ECOCON_COCON0 (1)
|
| 664 |
|
| 665 |
// EFLOCON bits -----
|
| 666 |
#define EFLOCON_FULDPXS (1<<2)
|
| 667 |
#define EFLOCON_FCEN1 (1<<1)
|
| 668 |
#define EFLOCON_FCEN0 (1)
|
| 669 |
|
| 670 |
|
| 671 |
|
| 672 |
// PHY bits
|
| 673 |
|
| 674 |
// PHCON1 bits ----------
|
| 675 |
#define PHCON1_PRST (1ul<<15)
|
| 676 |
#define PHCON1_PLOOPBK (1ul<<14)
|
| 677 |
#define PHCON1_PPWRSV (1ul<<11)
|
| 678 |
#define PHCON1_PDPXMD (1ul<<8)
|
| 679 |
|
| 680 |
// PHSTAT1 bits --------
|
| 681 |
#define PHSTAT1_PFDPX (1ul<<12)
|
| 682 |
#define PHSTAT1_PHDPX (1ul<<11)
|
| 683 |
#define PHSTAT1_LLSTAT (1ul<<2)
|
| 684 |
#define PHSTAT1_JBSTAT (1ul<<1)
|
| 685 |
|
| 686 |
// PHID2 bits --------
|
| 687 |
#define PHID2_PID24 (1ul<<15)
|
| 688 |
#define PHID2_PID23 (1ul<<14)
|
| 689 |
#define PHID2_PID22 (1ul<<13)
|
| 690 |
#define PHID2_PID21 (1ul<<12)
|
| 691 |
#define PHID2_PID20 (1ul<<11)
|
| 692 |
#define PHID2_PID19 (1ul<<10)
|
| 693 |
#define PHID2_PPN5 (1ul<<9)
|
| 694 |
#define PHID2_PPN4 (1ul<<8)
|
| 695 |
#define PHID2_PPN3 (1ul<<7)
|
| 696 |
#define PHID2_PPN2 (1ul<<6)
|
| 697 |
#define PHID2_PPN1 (1ul<<5)
|
| 698 |
#define PHID2_PPN0 (1ul<<4)
|
| 699 |
#define PHID2_PREV3 (1ul<<3)
|
| 700 |
#define PHID2_PREV2 (1ul<<2)
|
| 701 |
#define PHID2_PREV1 (1ul<<1)
|
| 702 |
#define PHID2_PREV0 (1ul)
|
| 703 |
|
| 704 |
// PHCON2 bits ----------
|
| 705 |
#define PHCON2_FRCLNK (1ul<<14)
|
| 706 |
#define PHCON2_TXDIS (1ul<<13)
|
| 707 |
#define PHCON2_JABBER (1ul<<10)
|
| 708 |
#define PHCON2_HDLDIS (1ul<<8)
|
| 709 |
|
| 710 |
// PHSTAT2 bits --------
|
| 711 |
#define PHSTAT2_TXSTAT (1ul<<13)
|
| 712 |
#define PHSTAT2_RXSTAT (1ul<<12)
|
| 713 |
#define PHSTAT2_COLSTAT (1ul<<11)
|
| 714 |
#define PHSTAT2_LSTAT (1ul<<10)
|
| 715 |
#define PHSTAT2_DPXSTAT (1ul<<9)
|
| 716 |
#define PHSTAT2_PLRITY (1ul<<5)
|
| 717 |
|
| 718 |
// PHIE bits -----------
|
| 719 |
#define PHIE_PLNKIE (1ul<<4)
|
| 720 |
#define PHIE_PGEIE (1ul<<1)
|
| 721 |
|
| 722 |
// PHIR bits -----------
|
| 723 |
#define PHIR_PLNKIF (1ul<<4)
|
| 724 |
#define PHIR_PGIF (1ul<<2)
|
| 725 |
|
| 726 |
// PHLCON bits -------
|
| 727 |
#define PHLCON_LACFG3 (1ul<<11)
|
| 728 |
#define PHLCON_LACFG2 (1ul<<10)
|
| 729 |
#define PHLCON_LACFG1 (1ul<<9)
|
| 730 |
#define PHLCON_LACFG0 (1ul<<8)
|
| 731 |
#define PHLCON_LBCFG3 (1ul<<7)
|
| 732 |
#define PHLCON_LBCFG2 (1ul<<6)
|
| 733 |
#define PHLCON_LBCFG1 (1ul<<5)
|
| 734 |
#define PHLCON_LBCFG0 (1ul<<4)
|
| 735 |
#define PHLCON_LFRQ1 (1ul<<3)
|
| 736 |
#define PHLCON_LFRQ0 (1ul<<2)
|
| 737 |
#define PHLCON_STRCH (1ul<<1)
|
| 738 |
|
| 739 |
#endif
|
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